M16C6C Datasheet, PDF (20/94 Pages) Renesas Technology Corp – RENESAS MCU

M16C/6C Group
3. Address Space
3.2 Memory Map
Special function registers (SFRs) are allocated from address 00000h to 003FFh and from 0D000h to
0D7FFh. Peripheral function control registers are located here. All blank areas within SFRs are reserved.
Do not access these areas.
Internal RAM is allocated from address 00400h higher, with 10 KB of internal RAM allocated from 00400h to
02BFFh. Internal RAM is used not only for data storage, but also for the stack area when subroutines are
called or when an interrupt request is accepted.
The internal ROM is flash memory. Three internal ROM areas are available: data flash, program ROM 1,
and program ROM 2.
The data flash is allocated from 0E000h to 0FFFFh. This data flash area is mostly used for data storage, but
can also store programs.
Program ROM 2 is allocated from 10000h to 13FFFh. Program ROM 1 is allocated from FFFFFh lower, with
the 64-KB program ROM 1 area allocated from address F0000h to FFFFFh.
The special page vectors are allocated from FFE00h to FFFD7h. They are used for the JMPS and JSRS
instructions. Refer to the M16C/60, M16C/20, M16C/Tiny Series Software Manual for details.
The fixed vector table for interrupts is allocated from FFFDCh to FFFFFh.
The 256 bytes beginning with the start address set in the INTB register compose the relocatable vector table
for interrupts.
Figure 3.2 shows the Memory Map.
00000h
Internal RAM
00400h
Size Address XXXXXh ^XXXXXh
12 KB
033FFh
SFR
Internal RAM
Reserved area
20 KB
31 KB
053FFh
07FFFh
0D000h
0D800h
0E000h
10000h
14000h
SFR
External area
Internal ROM
(data flash)
Internal ROM
(program ROM 2)
External area
13000h
13FF0h
13FFFh
On-chip debugger
monitor area
User boot code area
27000h
28000h
Reserved area
Program ROM 1
Size Address YYYYYh
128 KB
E0000h
80000h
256 KB
C0000h
384 KB
512 KB
A0000h
80000h
YYYYYh
External area
Reserved area
Internal ROM
(program ROM 1)
FFFFFh
Relocatable vector table
256 bytes beginning with the
start address set in the INTB
register
FFE00h
Special page vector table
FFFD8h
FFFDCh
Reserved area
Fixed vector table
Address for ID code stored
FFFFFh
OFS1 address
Notes:
1. Do not access reserved areas.
2. The figure above applies under the following conditions:
- Memory expansion mode
- The PM10 bit in the PM1 register is 1
(addresses 0E000h to 0FFFFh are used as data flash)
- The PRG2C0 bit in the PRG2C register is 0 (program ROM 2 enabled)
- The PM13 bit in the PM1 register is 1
(all areas in internal RAM, and the program ROM 1 area from 80000h are usable)
Figure 3.2 Memory Map
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
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