RX64M_16 Datasheet, PDF (85/228 Pages) Renesas Technology Corp – 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory

RX64M Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (14 / 67)
Address
0008 8022h
0008 8024h
0008 8026h
0008 8030h
0008 8032h
0008 8034h
0008 8036h
0008 8038h
0008 8040h
0008 8042h
0008 8044h
0008 8045h
0008 8046h
0008 8048h
0008 8100h
0008 8101h
0008 8108h
0008 8109h
0008 810Ah
0008 810Bh
0008 810Ch
0008 810Dh
0008 8110h
0008 8111h
0008 8112h
0008 8113h
0008 8114h
0008 8115h
0008 8116h
0008 8118h
0008 811Ah
0008 811Ch
0008 811Eh
0008 8120h
0008 8121h
0008 8122h
0008 8124h
0008 8125h
0008 8126h
0008 8128h
0008 812Ah
0008 8130h
0008 8131h
0008 8132h
0008 8134h
0008 8135h
0008 8136h
0008 8138h
0008 813Ah
0008 8140h
Module
Symbol Register Name
WDT WDT Control Register
WDT WDT Status Register
WDT WDT Reset Control Register
IWDT IWDT Refresh Register
IWDT IWDT Control Register
IWDT IWDT Status Register
IWDT IWDT Reset Control Register
IWDT IWDT Count Stop Control Register
DA
D/A Data Register 0
DA
D/A Data Register 1
DA
D/A Control Register
DA
DADRm Format Select Register
DA
D/A A/D Synchronous Start Control Register
DA
D/A Output Amplifier Control Register
TPUA Timer Start Register
TPUA Timer Synchronous Register
TPU0 Noise Filter Control Register
TPU1 Noise Filter Control Register
TPU2 Noise Filter Control Register
TPU3 Noise Filter Control Register
TPU4 Noise Filter Control Register
TPU5 Noise Filter Control Register
TPU0 Timer Control Register
TPU0 Timer Mode Register
TPU0 Timer I/O Control Register H
TPU0 Timer I/O Control Register L
TPU0 Timer Interrupt Enable Register
TPU0 Timer Status Register
TPU0 Timer Counter
TPU0 Timer General Register A
TPU0 Timer General Register B
TPU0 Timer General Register C
TPU0 Timer General Register D
TPU1 Timer Control Register
TPU1 Timer Mode Register
TPU1 Timer I/O Control Register
TPU1 Timer Interrupt Enable Register
TPU1 Timer Status Register
TPU1 Timer Counter
TPU1 Timer General Register A
TPU1 Timer General Register B
TPU2 Timer Control Register
TPU2 Timer Mode Register
TPU2 Timer I/O Control Register
TPU2 Timer Interrupt Enable Register
TPU2 Timer Status Register
TPU2 Timer Counter
TPU2 Timer General Register A
TPU2 Timer General Register B
TPU3 Timer Control Register
Register
Symbol
Number of Access Cycles
Number Access
of Bits Size ICLK PCLK
ICLK  PCLK
WDTCR
16
16
2, 3 PCLKB
2 ICLK
WDTSR
16
16
2, 3 PCLKB
2 ICLK
WDTRCR
8
8
2, 3 PCLKB
2 ICLK
IWDTRR
8
8
2, 3 PCLKB
2 ICLK
IWDTCR
16
16
2, 3 PCLKB
2 ICLK
IWDTSR
16
16
2, 3 PCLKB
2 ICLK
IWDTRCR
8
8
2, 3 PCLKB
2 ICLK
IWDTCSTPR
8
8
2, 3 PCLKB
2 ICLK
DADR0
16
16
2, 3 PCLKB
2 ICLK
DADR1
16
16
2, 3 PCLKB
2 ICLK
DACR
8
8
2, 3 PCLKB
2 ICLK
DADPR
8
8
2, 3 PCLKB
2 ICLK
DAADSCR
8
8
2, 3 PCLKB
2 ICLK
DAAMPCR
8
8
2, 3 PCLKB
2 ICLK
TSTR
8
8
2, 3 PCLKB
2 ICLK
TSYR
8
8
2, 3 PCLKB
2 ICLK
NFCR
8
8
2, 3 PCLKB
2 ICLK
NFCR
8
8
2, 3 PCLKB
2 ICLK
NFCR
8
8
2, 3 PCLKB
2 ICLK
NFCR
8
8
2, 3 PCLKB
2 ICLK
NFCR
8
8
2, 3 PCLKB
2 ICLK
NFCR
8
8
2, 3 PCLKB
2 ICLK
TCR
8
8
2, 3 PCLKB
2 ICLK
TMDR
8
8
2, 3 PCLKB
2 ICLK
TIORH
8
8
2, 3 PCLKB
2 ICLK
TIORL
8
8
2, 3 PCLKB
2 ICLK
TIER
8
8
2, 3 PCLKB
2 ICLK
TSR
8
8
2, 3 PCLKB
2 ICLK
TCNT
16
16
2, 3 PCLKB
2 ICLK
TGRA
16
16
2, 3 PCLKB
2 ICLK
TGRB
16
16
2, 3 PCLKB
2 ICLK
TGRC
16
16
2, 3 PCLKB
2 ICLK
TGRD
16
16
2, 3 PCLKB
2 ICLK
TCR
8
8
2, 3 PCLKB
2 ICLK
TMDR
8
8
2, 3 PCLKB
2 ICLK
TIOR
8
8
2, 3 PCLKB
2 ICLK
TIER
8
8
2, 3 PCLKB
2 ICLK
TSR
8
8
2, 3 PCLKB
2 ICLK
TCNT
16
16
2, 3 PCLKB
2 ICLK
TGRA
16
16
2, 3 PCLKB
2 ICLK
TGRB
16
16
2, 3 PCLKB
2 ICLK
TCR
8
8
2, 3 PCLKB
2 ICLK
TMDR
8
8
2, 3 PCLKB
2 ICLK
TIOR
8
8
2, 3 PCLKB
2 ICLK
TIER
8
8
2, 3 PCLKB
2 ICLK
TSR
8
8
2, 3 PCLKB
2 ICLK
TCNT
16
16
2, 3 PCLKB
2 ICLK
TGRA
16
16
2, 3 PCLKB
2 ICLK
TGRB
16
16
2, 3 PCLKB
2 ICLK
TCR
8
8
2, 3 PCLKB
2 ICLK
Related
Function
WDTA
WDTA
WDTA
IWDTa
IWDTa
IWDTa
IWDTa
IWDTa
R12DA
R12DA
R12DA
R12DA
R12DA
R12DA
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
TPUa
R01DS0173EJ0110 Rev.1.10
Oct 24, 2016
Page 85 of 228