RX64M_16 Datasheet, PDF (19/228 Pages) Renesas Technology Corp – 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory

RX64M Group
Table 1.4
Pin Functions (2/8)
Classifications
Pin Name
Bus control
RD#
WR#
WR0# to WR3#
BC0# to BC3#
ALE
EXDMA controller
Interrupt
Multi-function timer pulse
unit 3
WAIT#
CS0# to CS7#
CKE
SDCS#
RAS#
CAS#
WE#
DQM0 to DQM3
EDREQ0, EDREQ1
EDACK0, EDACK1
NMI
IRQ0 to IRQ15
MTIOC0A, MTIOC0B
MTIOC0C, MTIOC0D
MTIOC1A, MTIOC1B
MTIOC2A, MTIOC2B
Port output enable 3
MTIOC3A, MTIOC3B
MTIOC3C, MTIOC3D
MTIOC4A, MTIOC4B
MTIOC4C, MTIOC4D
MTIC5U, MTIC5V
MTIC5W
MTIOC6A, MTIOC6B
MTIOC6C, MTIOC6D
MTIOC7A, MTIOC7B
MTIOC7C, MTIOC7D
MTIOC8A, MTIOC8B
MTIOC8C, MTIOC8D
MTCLKA, MTCLKB
MTCLKC, MTCLKD
POE0#, POE4#, POE8#,
POE10#, POE11#
1. Overview
I/O
Description
Output Strobe signal which indicates that reading from the external bus
interface space is in progress
Output Strobe signal which indicates that writing to the external bus
interface space is in progress, in 1-write strobe mode
Output Strobe signals which indicate that either group of data bus pins
(D7 to D0, D15 to D8, D23 to D16 and D31 to D24) is valid in
writing to the external bus interface space, in byte strobe mode
Output
Strobe signals which indicate that either group of data bus pins
(D7 to D0, D15 to D8, D23 to D16 and D31 to D24) is valid in
access to the external bus interface space, in 1-write strobe
mode
Output Address latch signal when address/data multiplexed bus is
selected
Input Input pin for wait request signals in access to the external space
Output Select signals for CS areas
Output SDRAM clock enable signal
Output SDRAM chip select signal
Output SDRAM row address strobe signal
Output SDRAM column address strove signal
Output SDRAM write enable pin
Output SDRAM I/O data mask enable signals
Input External DMA transfer request pins
Output Single address transfer acknowledge signals
Input Non-maskable interrupt request pin
Input Maskable interrupt request pins
I/O
The TGRA0 to TGRD0 input capture input/output compare
output/PWM output pins
I/O
The TGRA1 and TGRB1 input capture input/output compare
output/PWM output pins
I/O
The TGRA2 and TGRB2 input capture input/output compare
output/PWM output pins
I/O
The TGRA3 to TGRD3 input capture input/output compare
output/PWM output pins
I/O
The TGRA4 to TGRD4 input capture input/output compare
output/PWM output pins
Input
The TGRU5, TGRV5, and TGRW5 input capture input/dead
time compensation input pins
I/O
The TGRA6 to TGRD6 input capture input/output compare
output/PWM output pins
I/O
The TGRA7 to TGRD7 input capture input/output compare
output/PWM output pins
I/O
The TGRA8 to TGRD8 input capture input/output compare
output/PWM output pins
Input
Input pins for external clock signals or for phase counting mode
clock signals
Input
Input pins for request signals to place the MTU or GPT in the
high impedance state
R01DS0173EJ0110 Rev.1.10
Oct 24, 2016
Page 19 of 228