RX64M_16 Datasheet, PDF (186/228 Pages) Renesas Technology Corp – 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory

RX64M Group
5. Electrical Characteristics
Table 5.35 QSPI Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T_a = T_opr
Output load conditions: V_OH = VCC × 0.5, V_OL = VCC × 0.5, C = 30 pF
High-drive output is selected by the driving ability control register.
Item
Symbol
Min.
Max.
Unit*¹
Test
Conditions*²
QSPI
QSPCLK clock cycle
Data input setup time
Data input hold time
SS setup time
SS hold time
Data output delay time
Data output hold time
Successive transmission delay time
t_QScyc
t_Su
t_IH
t_LEAD
t_LAG
t_OD
t_OH
t_TD
2
4080
t_PBcyc Figure 5.53
6.5
—
ns
Figure 5.54,
5
—
ns
Figure 5.55
1.5
8.5
t_QScyc
1
8
t_QScyc
—
10.0
ns
–5
—
ns
1
8
t_QScyc
Note 1. t_PBcyc: PCLKB cycle
Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc.) to indicate group membership appended to their names as groups.
For the QSPI interface, the AC portion of the electrical characteristics is measured for each group.
QSPCLK
output
Figure 5.53 QSPI Clock Timing
t_QScyc
QSSL
output
QSPCLK
CPOL = 0
output
QSPCLK
CPOL = 1
output
QMI,
QIO0 to QIO3
input
QMO,
QIO0 to QIO3
output
tLEAD
tLAG
tSU
tIH
MSB IN
DATA
tOH
LSB IN
tOD
MSB OUT
DATA
LSB OUT
tTD
IDLE
Figure 5.54 Transmit/Receive Timing (CPHA = 0)
R01DS0173EJ0110 Rev.1.10
Oct 24, 2016
Page 186 of 228