RX64M_16 Datasheet, PDF (115/228 Pages) Renesas Technology Corp – 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory

RX64M Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (44 / 67)
Address
000A 009Ah
Module
Symbol Register Name
USB0 Pipe3 Transaction Counter Register
Register
Symbol
PIPE3TRN
000A 009Ch USB0 Pipe4 Transaction Counter Enable Register
PIPE4TRE
000A 009Eh USB0 Pipe4 Transaction Counter Register
PIPE4TRN
000A 00A0h USB0 Pipe5 Transaction Counter Enable Register
PIPE5TRE
000A 00A2h USB0 Pipe5 Transaction Counter Register
PIPE5TRN
000A 00D0h USB0 Device Address 0 Configuration Register
DEVADD0
000A 00D2h USB0 Device Address 1 Configuration Register
DEVADD1
000A 00D4h USB0 Device Address 2 Configuration Register
DEVADD2
000A 00D6h USB0 Device Address 3 Configuration Register
DEVADD3
000A 00D8h USB0 Device Address 4 Configuration Register
DEVADD4
000A 00DAh USB0 Device Address 5 Configuration Register
DEVADD5
000A 00F0h USB0 PHY Cross Point Adjustment Register
PHYSLEW
000A 0400h USB
Deep Standby USB Transceiver Control/Pin
Monitoring Register
DPUSR0R
000A 0404h USB
Deep Standby USB Suspend/Resume Interrupt
Register
DPUSR1R
000A 0500h PDC PDC Control Register 0
000A 0504h PDC PDC Control Register 1
000A 0508h PDC PDC Status Register
000A 050Ch PDC PDC Pin Monitor Register
000A 0510h PDC PDC Receive Data Register
000A 0514h PDC Vertical Capture Register
000A 0518h PDC Horizontal Capture Register
000C 0000h EDMAC EDMAC Mode Register
0
000C 0008h EDMAC EDMAC Transmit Request Register
0
000C 0010h EDMAC EDMAC Receive Request Register
0
000C 0018h EDMAC Transmit Descriptor List Start Address Register
0
000C 0020h EDMAC Receive Descriptor List Start Address Register
0
000C 0028h EDMAC ETHERC/EDMAC Status Register
0
000C 0030h EDMAC ETHERC/EDMAC Status Interrupt Enable Register
0
000C 0038h EDMAC ETHERC/EDMAC Transmit/Receive Status Copy
0
Enable Register
000C 0040h EDMAC Missed-Frame Counter Register
0
000C 0048h EDMAC Transmit FIFO Threshold Register
0
PCCR0
PCCR1
PCSR
PCMONR
PCDR
VCR
HCR
EDMR
EDTRR
EDRRR
TDLAR
RDLAR
EESR
EESIPR
TRSCER
RMFCR
TFTR
Number of Access Cycles
Number Access
of Bits Size ICLK PCLK
ICLK  PCLK
Related
Function
16
16
9 PCLKB
or more
Frequency with 1 + 9 USBb
× (frequency ratio of
ICLK/PCLKB)*⁵
16
16
9 PCLKB
or more
Frequency with 1 + 9 USBb
× (frequency ratio of
ICLK/PCLKB)*⁵
16
16
9 PCLKB
or more
Frequency with 1 + 9 USBb
× (frequency ratio of
ICLK/PCLKB)*⁵
16
16
9 PCLKB
or more
Frequency with 1 + 9 USBb
× (frequency ratio of
ICLK/PCLKB)*⁵
16
16
9 PCLKB
or more
Frequency with 1 + 9 USBb
× (frequency ratio of
ICLK/PCLKB)*⁵
16
16
9 PCLKB
or more
Frequency with 1 + 9 USBb
× (frequency ratio of
ICLK/PCLKB)*⁵
16
16
9 PCLKB
or more
Frequency with 1 + 9 USBb
× (frequency ratio of
ICLK/PCLKB)*⁵
16
16
9 PCLKB
or more
Frequency with 1 + 9 USBb
× (frequency ratio of
ICLK/PCLKB)*⁵
16
16
9 PCLKB
or more
Frequency with 1 + 9 USBb
× (frequency ratio of
ICLK/PCLKB)*⁵
16
16
9 PCLKB
or more
Frequency with 1 + 9 USBb
× (frequency ratio of
ICLK/PCLKB)*⁵
16
16
9 PCLKB
or more
Frequency with 1 + 9 USBb
× (frequency ratio of
ICLK/PCLKB)*⁵
32
32
9 PCLKB
or more
Frequency with 1 + 9 USBb
× (frequency ratio of
ICLK/PCLKB)*⁵
32
32
9 PCLKB
or more
Frequency with 1 + 9 USBb
× (frequency ratio of
ICLK/PCLKB)*⁵
32
32
9 PCLKB
or more
Frequency with 1 + 9 USBb
× (frequency ratio of
ICLK/PCLKB)*⁵
32
32
2, 3 PCLKB
2 ICLK
PDC
32
32
2, 3 PCLKB
2 ICLK
PDC
32
32
2, 3 PCLKB
2 ICLK
PDC
32
32
2, 3 PCLKB
2 ICLK
PDC
32
32
2, 3 PCLKB
2 ICLK
PDC
32
32
2, 3 PCLKB
2 ICLK
PDC
32
32
2, 3 PCLKB
2 ICLK
PDC
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
R01DS0173EJ0110 Rev.1.10
Oct 24, 2016
Page 115 of 228