RX64M_16 Datasheet, PDF (153/228 Pages) Renesas Technology Corp – 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory

RX64M Group
5. Electrical Characteristics
5.3.3
Timing of Recovery from Low Power Consumption Modes
Table 5.18 Timing of Recovery from Low Power Consumption Modes (1)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
T_a = T_opr
Item
Recovery time
after
cancellation of
software
standby
mode*¹
Crystal
resonator
connected to
main clock
oscillator
Main clock
oscillator
operating
Main clock
oscillator and
PLL circuit
operating
External clock Main clock
input to main oscillator
clock oscillator operating
Main clock
oscillator and
PLL circuit
operating
Sub-clock oscillator operating
High-speed
on-chip
oscillator
operating
High-speed
on-chip
oscillator
operating
High-speed
on-chip
oscillator
operating and
PLL circuit
operating
Low-speed on-chip oscillator
operating*⁴
Symbol Min. Typ.
t_SBYMC — —
t_SBYPC
t_SBYEX
t_SBYPE
t_SBYSC
t_SBYHO
t_SBYPH
t_SBYLO
Max.
t_SBYOSCWT*²
t_SBYSEQ*³
Unit
Test
Conditions
{( MSTS[7:0] bits × 100 μs + 7/f_ICLK + μs Figure 5.12
32 ) + 76 } / 0.216
2n/f_MAIN
{( MSTS[7:0] bits × 100 μs + 7/f_ICLK +
32 ) + 138 } / 0.216
2n/f_PLL
352
100 μs + 7/f_ICLK +
2n/f_EXMAIN
639
100 μs + 7/f_ICLK +
2n/f_PLL
{( SSTS[7:0] bits ×
16384 ) + 13 } /
0.216 + 10/f_FCLK
454
100 μs + 4/f_ICLK +
2n/f_SUB
100 μs + 7/f_ICLK +
2n/f_HOCO
741
100 μs + 7/f_ICLK +
2n/f_PLL
338
100 μs + 7/f_ICLK +
2n/f_LOCO
Note 1.
Note 2.
Note 3.
Note 4.
The time for return after release from software standby is determined by the value obtained by adding the oscillation stabilization
waiting time (t_SBYOSCWTO) and the time required for operations by the software standby release sequencer (t_SBYSEQ).
When several oscillators were running before the transition to software standby, the greatest value of the oscillation stabilization
waiting time t_SBYOSCWT is selected.
For n, the greatest value is selected from among the internal clock division settings.
This condition applies when f_ICLK:f_FCLK = 1:1, 2:1, or 4:1.
R01DS0173EJ0110 Rev.1.10
Oct 24, 2016
Page 153 of 228