RX64M_16 Datasheet, PDF (182/228 Pages) Renesas Technology Corp – 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory

RX64M Group
5. Electrical Characteristics
Table 5.34 Simple SPI Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T_a = T_opr
Output load conditions: V_OH = VCC × 0.5, V_OL = VCC × 0.5, C = 30 pF
High-drive output is selected by the driving ability control register.
Item
Simple
SPI
SCK clock cycle output (master)
SCK clock cycle input (slave)
SCK clock high pulse width
SCK clock low pulse width
SCK clock rise/fall time
Data input setup time
Data input hold time
SS input setup time
SS input hold time
Data output delay time
Data output hold time
Data rise/fall time
SS input rise/fall time
Slave access time
Slave output release time
Note 1. t_PBcyc: PCLKB cycle
Symbol
t_SPcyc
t_SPCKWH
t_SPCKWL
t_SPCKr, t_SPCKf
t_SU
t_H
t_LEAD
t_LAG
t_OD
t_OH
t_Dr, t_Df
t_SSLr, t_SSLf
t_SA
t_REL
Min.
4
8
0.4
0.4
—
33.3
33.3
1
1
—
–10
—
—
—
—
Max.
65536
65536
0.6
0.6
20
—
—
—
—
33.3
—
16.6
16.6
5
5
Unit*¹
t_PBcyc
Test
Conditions
Figure 5.46
t_SPcyc
t_SPcyc
ns
ns
ns
t_SPcyc
t_SPcyc
ns
ns
ns
ns
t_PBcyc
t_PBcyc
Figure 5.47 to
Figure 5.52
Figure 5.51,
Figure 5.52
RSPI
RSPCKA
master select
output
Simple SPI
SCKn
master select
output
V_OH
t_SPCKWH
V_IH
RSPCKA
SCKn
slave select input slave select input
(n = 0 to 7, 12)
t_SPCKWH
t_SPCKr
t_SPCKf
V_OH
V_OL
V_OL
t_SPCKWL
V_OH
t_SPcyc
V_OH
V_OL
t_SPCKr
V_IH
V_IL
V_IL
t_SPCKWL
V_IH
t_SPcyc
t_SPCKf
V_IH
V_IL
V_OH = 0.7 × VCC, V_OL = 0.3 × VCC, V_IH = 0.7 × VCC, V_IL = 0.3 × VCC
Figure 5.46 RSPI Clock Timing and Simple SPI Clock Timing
R01DS0173EJ0110 Rev.1.10
Oct 24, 2016
Page 182 of 228