RX64M_16 Datasheet, PDF (2/228 Pages) Renesas Technology Corp – 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory

RX64M Group
1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different
packages.
Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs
depending on the pin number on the package and the code flash memory capacity. For details, see Table 1.2,
Comparison of Functions for Different Packages.
Table 1.1
Outline of Specifications (1/9)
Classification Module/Function
CPU
CPU
Memory
FPU
Code flash memory
Data flash memory
RAM
Unique ID
RAM with ECC
Standby RAM
Operating modes
Description
 Maximum operating frequency: 120 MHz
 32-bit RX CPU (RXv2)
 Minimum instruction execution time: One instruction per state (cycle of the system
clock)
 Address space: 4-Gbyte linear
 Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Ten 32-bit registers
Accumulator: Two 72-bit registers
 Basic instructions: 75
 Floating-point instructions: 11
 DSP instructions: 23
 Addressing modes: 11
 Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
 On-chip 32-bit multiplier: 32 × 32 → 64 bits
 On-chip divider: 32 / 32 → 32 bits
 Barrel shifter: 32 bits
 Single precision (32-bit) floating point
 Data types and floating-point exceptions in conformance with the IEEE754 standard
 Capacity: 2 Mbytes, 2.5 Mbytes, 3 Mbytes, 4 Mbytes
 120 MHz, no-wait access
 On-board programming: Four types
 Off-board programming (parallel programmer mode)
 The trusted memory (TM) function protects against the reading of programs from blocks
8 and 9.
 Capacity: 64 Kbytes
 Programming/erasing: 100,000 times
 Capacity: 512 Kbytes
 120 MHz, no-wait access
 SED (single error detection)
 12-byte length ID unique to the device
 Capacity: 32 Kbytes
 120 MHz, single wait access
 SEC-DED (single error correction/double error detection)
 Capacity: 8 Kbytes
 Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access
 Operating modes by the mode-setting pins at the time of release from the reset state
Single-chip mode
Boot mode (for the SCI interface)
Boot mode (for the USB interface)
User boot mode
 Selection of operating mode by register setting
Single-chip mode, user boot mode
On-chip ROM disabled extended mode
On-chip ROM enabled extended mode
 Endian selectable
R01DS0173EJ0110 Rev.1.10
Oct 24, 2016
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