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RX64M_16 Datasheet, PDF (5/228 Pages) Renesas Technology Corp – 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory | |||
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RX64M Group
1. Overview
Table 1.1
Outline of Specifications (4/9)
Classification
Timers
Timers
Module/Function
Description
16-bit timer pulse unit
(TPUa)
ï· (16 bits à 6 channels) à 1 unit
ï· Maximum of 16 pulse-input/output possible
ï· Select from among seven or eight counter-input clock signals for each channel
ï· Input capture/output compare function
ï· Output of PWM waveforms in up to 15 phases in PWM mode
ï· Support for buffered operation, phase-counting mode (two phase encoder input) and
cascade-connected operation (32 bits à 2 channels) depending on the channel.
ï· PPG output trigger can be generated
ï· Capable of generating conversion start triggers for the A/D converters
ï· Digital filtering of signals from the input capture pins
ï· Event linking by the ELC
Multifunction timer pulse
unit (MTU3a)
ï· 9 channels (16 bits à 8 channels, 32 bits à 1 channel)
ï· Maximum of 28 pulse-input/output and 3 pulse-input possible
ï· Select from among 14 counter-input clock signals for each channel (PCLKA/1, PCLKA/
2, PCLKA/4, PCLKA/8, PCLKA/16, PCLKA/32, PCLKA/64, PCLKA/256, PCLKA/1024,
MTCLKA, MTCLKB, MTCLKC, MTCLKD, MTIOC1A)
14 of the signals are available for channel 0, 12 are available for channel 2, 11 are
available for channels 1, 3, 4, 6 to 8, and 10 are available for channel 5.
ï· Input capture function
ï· 39 output compare/input capture registers
ï· Counter clear operation (synchronous clearing by compare match/input capture)
ï· Simultaneous writing to multiple timer counters (TCNT)
ï· Simultaneous register input/output by synchronous counter operation
ï· Buffered operation
ï· Support for cascade-connected operation
ï· 43 interrupt sources
ï· Automatic transfer of register data
ï· Pulse output mode
Toggle/PWM/complementary PWM/reset-synchronized PWM
ï· Complementary PWM output mode
Outputs non-overlapping waveforms for controlling 3-phase inverters
Automatic specification of dead times
PWM duty cycle: Selectable as any value from 0% to 100%
Delay can be applied to requests for A/D conversion.
Non-generation of interrupt requests at peak or trough values of counters can be
selected.
Double buffer configuration
ï· Reset synchronous PWM mode
Three phases of positive and negative PWM waveforms can be output with desired duty
cycles.
ï· Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2)
ï· Counter functionality for dead-time compensation
ï· Generation of triggers for A/D converter conversion
ï· A/D converter start triggers can be skipped
ï· Digital filter function for signals on the input capture and external counter clock pins
ï· PPG output trigger can be generated
ï· Event linking by the ELC
Port output enable 3
(POE3a)
ï· Control of the high-impedance state of the MTU3/GPT's waveform output pins
ï· 5 pins for input from signal sources: POE0, POE4, POE8, POE10, POE11
ï· Initiation on detection of short-circuited outputs (detection of simultaneous PWM output
to the active level)
ï· Initiation by oscillation-stoppage detection or software
ï· Additional programming of output control target pins is enabled
R01DS0173EJ0110 Rev.1.10
Oct 24, 2016
Page 5 of 228
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