RX64M_16 Datasheet, PDF (112/228 Pages) Renesas Technology Corp – 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory

RX64M Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (41 / 67)
Address
Module
Symbol Register Name
0009 1852h CAN1 Mailbox Search Status Register
0009 1853h CAN1 Mailbox Search Mode Register
0009 1854h CAN1 Time Stamp Register
0009 1856h CAN1 Acceptance Filter Support Register
0009 1858h CAN1 Test Control Register
0009 2200h to CAN2 Mailbox Registers 0 to 31
0009 23FFh
0009 2400h to CAN2 Mask Registers 0 to 7
0009 241Fh
0009 2420h CAN2 FIFO Received ID Compare Register 0
0009 2424h CAN2 FIFO Received ID Compare Register 1
0009 2428h CAN2 Mask Invalid Register
0009 242Ch CAN2 Mailbox Interrupt Enable Register
0009 2820h to CAN2
0009 283Fh
0009 2840h CAN2
0009 2842h CAN2
0009 2844h CAN2
Message Control Registers 0 to 31
Control Register
Status Register
Bit Configuration Register
0009 2848h
0009 2849h
0009 284Ah
0009 284Bh
0009 284Ch
0009 284Dh
0009 284Eh
0009 284Fh
0009 2850h
0009 2851h
0009 2852h
0009 2853h
0009 2854h
0009 2856h
0009 2858h
0009 4200h
0009 4204h
0009 4208h
0009 4210h
0009 4214h
0009 4218h
0009 421Ch
0009 4220h
0009 4224h
0009 4280h
0009 4284h
0009 4288h
0009 4290h
0009 4294h
0009 4298h
0009 429Ch
CAN2 Receive FIFO Control Register
CAN2 Receive FIFO Pointer Control Register
CAN2 Transmit FIFO Control Register
CAN2 Transmit FIFO Pointer Control Register
CAN2 Error Interrupt Enable Register
CAN2 Error Interrupt Factor Judge Register
CAN2 Receive Error Count Register
CAN2 Transmit Error Count Register
CAN2 Error Code Store Register
CAN2 Channel Search Support Register
CAN2 Mailbox Search Status Register
CAN2 Mailbox Search Mode Register
CAN2 Time Stamp Register
CAN2 Acceptance Filter Support Register
CAN2 Test Control Register
CMTW0 Timer Start Register
CMTW0 Timer Control Register
CMTW0 Timer I/O Control Register
CMTW0 Timer Counter
CMTW0 Compare Match Constant Register
CMTW0 Input Capture Register 0
CMTW0 Input Capture Register 1
CMTW0 Output Compare Register 0
CMTW0 Output Compare Register 1
CMTW1 Timer Start Register
CMTW1 Timer Control Register
CMTW1 Timer I/O Control Register
CMTW1 Timer Counter
CMTW1 Compare Match Constant Register
CMTW1 Input Capture Register 0
CMTW1 Input Capture Register 1
Register
Symbol
MSSR
MSMR
TSR
AFSR
TCR
MB0 to 31
Number of Access Cycles
Number Access
of Bits Size ICLK PCLK
ICLK  PCLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
16
16
2, 3 PCLKB
2 ICLK
16
8, 16
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
128
8, 16,
32*⁶
2, 3 PCLKB
2 ICLK
MKR0 to 7
32
8, 16,
32
2, 3 PCLKB
2 ICLK
FIDCR0
32
8, 16,
32
FIDCR1
32
8, 16,
32
MKIVLR
32
8, 16,
32
MIER
32
8, 16,
32
MCTL0 to 31
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
CTLR
STR
BCR
RFCR
RFPCR
TFCR
TFPCR
EIER
EIFR
RECR
TECR
ECSR
CSSR
MSSR
MSMR
TSR
AFSR
TCR
CMWSTR
CMWCR
CMWIOR
CMWCNT
CMWCOR
CMWICR0
CMWICR1
CMWOCR0
CMWOCR1
CMWSTR
CMWCR
CMWIOR
CMWCNT
CMWCOR
CMWICR0
CMWICR1
16
8, 16
16
8, 16
32
8, 16,
32
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
16
8, 16
16
8, 16
8
8
16
16
16
16
16
16
32
32
32
32
32
32
32
32
32
32
32
32
16
16
16
16
16
16
32
32
32
32
32
32
32
32
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
Related
Function
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CMTW
CMTW
CMTW
CMTW
CMTW
CMTW
CMTW
CMTW
CMTW
CMTW
CMTW
CMTW
CMTW
CMTW
CMTW
CMTW
R01DS0173EJ0110 Rev.1.10
Oct 24, 2016
Page 112 of 228