RX64M_16 Datasheet, PDF (129/228 Pages) Renesas Technology Corp – 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory

RX64M Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (58 / 67)
Address
Module
Symbol Register Name
Register
Symbol
Number of Access Cycles
Number Access
of Bits Size ICLK PCLK
ICLK  PCLK
000C 4900h EPTPC PTP-primary Message Destination MAC Address
PPMACRU
32
32
9 to 211 PCLKA
2 to 106 ICLK
0
Setting Registers
000C 4904h EPTPC PTP-primary Message Destination MAC Address
0
Setting Registers
PPMACRL
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4908h EPTPC PTP-pdelay Message MAC Address Setting Registers PDMACRU
32
32
9 to 211 PCLKA
2 to 106 ICLK
0
000C 490Ch EPTPC PTP-pdelay Message MAC Address Setting Registers PDMACRL
0
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4910h EPTPC PTP Message EtherType Setting Register
0
PETYPER
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4920h EPTPC PTP-primary Message Destination IP Address Setting PPIPR
0
Register
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4924h EPTPC PTP-pdelay Message Destination IP Address Setting PDIPR
0
Register
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4928h EPTPC PTP event Message TOS Setting Register
0
PETOSR
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 492Ch EPTPC PTP general Message TOS Setting Register
0
PGTOSR
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4930h EPTPC PTP-primary Message TTL Setting Register
0
PPTTLR
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4934h EPTPC PTP-pdelay Message TTL Setting Register
0
PDTTLR
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4938h EPTPC PTP event Message UDP Destination Port Number PEUDPR
0
Setting Register
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 493Ch EPTPC PTP general Message UDP Destination Port Number PGUDPR
0
Setting Register
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4940h EPTPC Frame Reception Filter Setting Register
0
FFLTR
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4960h EPTPC Frame Reception Filter MAC Address 0 Setting
0
Registers
FMAC0RU
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4964h EPTPC Frame Reception Filter MAC Address 0 Setting
0
Registers
FMAC0RL
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4968h EPTPC Frame Reception Filter MAC Address 1 Setting
0
Registers
FMAC1RU
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 496Ch EPTPC Frame Reception Filter MAC Address 1 Setting
0
Registers
FMAC1RL
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 49C0h EPTPC Asymmetric Delay Setting Register
0
DASYMRU
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 49C4h EPTPC Asymmetric Delay Setting Register
0
DASYMRL
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 49C8h EPTPC Timestamp Latency Setting Register
0
TSLATR
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 49CCh EPTPC SYNFP Operation Setting Register
0
SYCONFR
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 49D0h EPTPC SYNFP Frame Format Setting Register
0
SYFORMR
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 49D4h EPTPC Response Message Reception Timeout Register
0
RSTOUTR
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4C00h EPTPC SYNFP Status Register
1
SYSR
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4C04h EPTPC SYNFP Status Notification Permission Register
1
SYIPR
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4C10h EPTPC SYNFP MAC Address Registers
1
SYMACRU
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4C14h EPTPC SYNFP MAC Address Registers
1
SYMACRL
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4C1Ch EPTPC SYNFP Local IP Address Register
1
SYIPADDRR
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4C40h EPTPC SYNFP Specification Version Setting Register
1
SYSPVRR
32
32
9 to 211 PCLKA
2 to 106 ICLK
000C 4C44h EPTPC SYNFP Domain Number Setting Register
1
SYDOMR
32
32
9 to 211 PCLKA
2 to 106 ICLK
Related
Function
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
EPTPC
R01DS0173EJ0110 Rev.1.10
Oct 24, 2016
Page 129 of 228