UPD70F3741GC Datasheet, PDF (841/889 Pages) Renesas Technology Corp – RENESAS MCU V850ES/JG3 Microcontrollers

V850ES/JG3
APPENDIX D INSTRUCTION SET LIST
(3) Register symbols used in operations
Register Symbol
←
GR [ ]
SR [ ]
zero-extend (n)
sign-extend (n)
load-memory (a, b)
store-memory (a, b, c)
load-memory-bit (a, b)
store-memory-bit (a, b, c)
saturated (n)
result
Byte
Halfword
Word
+
–
ll
×
÷
%
AND
OR
XOR
NOT
logically shift left by
logically shift right by
arithmetically shift right by
Explanation
Input for
General-purpose register
System register
Expand n with zeros until word length.
Expand n with signs until word length.
Read size b data from address a.
Write data b into address a in size c.
Read bit b of address a.
Write c to bit b of address a.
Execute saturated processing of n (n is a 2’s complement).
If, as a result of calculations,
n ≥ 7FFFFFFFH, let it be 7FFFFFFFH.
n ≤ 80000000H, let it be 80000000H.
Reflects the results in a flag.
Byte (8 bits)
Half word (16 bits)
Word (32 bits)
Addition
Subtraction
Bit concatenation
Multiplication
Division
Remainder from division results
Logical product
Logical sum
Exclusive OR
Logical negation
Logical shift left
Logical shift right
Arithmetic shift right
(4) Register symbols used in execution clock
Register Symbol
i
r
l
Explanation
If executing another instruction immediately after executing the first instruction (issue).
If repeating execution of the same instruction immediately after executing the first instruction (repeat).
If using the results of instruction execution in the instruction immediately after the execution (latency).
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 825 of 870