UPD70F3741GC Datasheet, PDF (513/889 Pages) Renesas Technology Corp – RENESAS MCU V850ES/JG3 Microcontrollers

V850ES/JG3
(2) Operation timing
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
CBnTSF bit
INTCBnR signal
SCKBn pin
SOBn pin
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(1) (4) (5)
(6) (7)
(8)
(2)
(3)
(1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) =
fXX/2, and master mode.
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write C1H to the CBnCTL0 register, and select the transmission mode and MSB first at the same time
as enabling the operation of the communication clock (fCCLK).
(4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and
transmission is started.
(5) When transmission is started, output the serial clock to the SCKBn pin, and output the transmit data
from the SOBn pin in synchronization with the serial clock.
(6) When transmission of the transfer data length set with the CBnCTL2 register is completed, stop the
serial clock output and transmit data output, generate the reception completion interrupt request signal
(INTCBnR) at the last edge of the serial clock, and clear the CBnTSF bit to 0.
(7) To continue transmission, start the next transmission by writing the transmit data to the CBnTX register
again after the INTCBnR signal is generated.
(8) To end transmission, write the CBnCTL0.CBnPWR bit = 0 and the CBnCTL0.CBnTXE bit = 0.
Remark n = 0 to 4
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 497 of 870