UPD70F3741GC Datasheet, PDF (177/889 Pages) Renesas Technology Corp – RENESAS MCU V850ES/JG3 Microcontrollers

V850ES/JG3
CHAPTER 5 BUS CONTROL FUNCTION
5.6 Wait Function
5.6.1 Programmable wait function
(1) Data wait control register 0 (DWC0)
To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle
that is executed for each memory block space.
The number of wait states can be programmed by using the DWC0 register . Immediately after system reset, 7
data wait states are inserted for all the blocks.
The DWC0 register can be read or written in 16-bit units.
Reset sets this register to 7777H.
Cautions 1. The internal ROM and internal RAM areas are not subject to programmable wait, and are
always accessed without a wait state. The on-chip peripheral I/O area is also not subject to
programmable wait, and only wait control from each peripheral function is performed.
2. Write to the DWC0 register after reset, and then do not change the set values. Also, do not
access an external memory area until the initial settings of the DWC0 register are complete.
3. When the V850ES/JG3 is used in separate bus mode and operated at fXX > 20 MHz, be sure to
insert one or more waits.
After reset: 7777H R/W
15
14
DWC0
0
DW32
Address: FFFFF484H
13
12
11
DW31 DW30
0
Memory block 3
7
6
5
4
3
0
DW12 DW11 DW10
0
Memory block 1
10
DW22
9
DW21
8
DW20
Memory block 2
2
1
0
DW02 DW01 DW00
Memory block 0
DWn2
0
0
0
0
1
1
1
1
DWn1
0
0
1
1
0
0
1
1
DWn0
0
1
0
1
0
1
0
1
Number of wait states inserted in
memory block n space (n = 0 to 3)
Multiplexed bus
Separate bus
None
fXX ≤ 20 MHz
fXX > 20 MHz
None
Setting prohibited
1
2
3
4
5
6
7
Caution Be sure to clear bits 15, 11, 7, and 3 to “0”.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 161 of 870