UPD70F3741GC Datasheet, PDF (664/889 Pages) Renesas Technology Corp – RENESAS MCU V850ES/JG3 Microcontrollers

V850ES/JG3
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 19-7. Example of Processing in Which Another Interrupt Request Signal Is Issued
While an Interrupt Is Being Serviced (1/2)
Main routine
EI
Interrupt request a
(level 3)
Interrupt
request b
(level 2)
Servicing of a
EI
Servicing of b
Interrupt request b is acknowledged because the
priority of b is higher than that of a and interrupts are
enabled.
Servicing of c
Interrupt request c
(level 3)
Interrupt request d
(level 2)
Servicing of d
Although the priority of interrupt request d is higher
than that of c, d is held pending because interrupts
are disabled.
Interrupt request e
(level 2)
Servicing of e
EI
Interrupt request f
(level 3)
Servicing of f
Interrupt request f is held pending even if interrupts are
enabled because its priority is lower than that of e.
Interrupt request g
(level 1)
Servicing of g
EI
Interrupt request h
(level 1)
Servicing of h
Interrupt request h is held pending even if interrupts are
enabled because its priority is the same as that of g.
Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be
saved before executing the EI instruction. When returning from multiple interrupt servicing,
restore the values of EIPC and EIPSW after executing the DI instruction.
Remarks 1. a to u in the figure are the temporary names of interrupt request signals shown for the sake of
explanation.
2. The default priority in the figure indicates the relative priority between two interrupt request
signals.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 648 of 870