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| UPD70F3741GC Datasheet, PDF (626/889 Pages) Renesas Technology Corp – RENESAS MCU V850ES/JG3 Microcontrollers | |||
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V850ES/JG3
CHAPTER 17 I2C BUS
Figure 17-24. Example of Slave to Master Communication
(When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (2/3)
Processing by master device
IICn
ACKDn
STDn L
SPDn L
WTIMn L
ACKEn H
MSTSn H
STTn L
SPTn L
WRELn
INTIICn
TRCn L Receive
Transfer lines
SCL0n 8 9
SDA0n D0 ACK
(b) Data
IICn â FFH Note
Note
123456789
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Processing by slave device
IICn
ACKDn
STDn L
SPDn L
WTIMn H
ACKEn H
MSTSn L
STTn L
SPTn L
WRELn L
INTIICn
TRCn H Transmit
IICn â data
Note To cancel master wait, write FFH to IICn or set WRELn.
Remark n = 0 to 2
IICn â FFH Note
Note
1 23
D7 D6 D5
IICn â data
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 610 of 870
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