UPD70F3741GC Datasheet, PDF (556/889 Pages) Renesas Technology Corp – RENESAS MCU V850ES/JG3 Microcontrollers

V850ES/JG3
CHAPTER 17 I²C BUS
(7) Interrupt request signal generator
This circuit controls the generation of interrupt request signals (INTIICn).
An I²C interrupt is generated following either of two triggers.
• Falling edge of eighth or ninth clock of the serial clock (set by IICCn.WTIMn bit)
• Interrupt occurrence due to stop condition detection (set by IICCn.SPIEn bit)
Remark n = 0 to 2
(8) Serial clock controller
In master mode, this circuit generates the clock output via the SCL0n pin from the sampling clock (n = 0 to 2).
(9) Serial clock wait controller
This circuit controls the wait timing.
(10) ACK generator, stop condition detector, start condition detector, and ACK detector
These circuits are used to generate and detect various statuses.
(11) Data hold time correction circuit
This circuit generates the hold time for data corresponding to the falling edge of the SCL0n pin.
(12) Start condition generator
A start condition is generated when the IICCn.STTn bit is set.
However, in the communication reservation disabled status (IICFn.IICRSVn bit = 1), this request is ignored and the
IICFn.STCFn bit is set to 1 if the bus is not released (IICFn.IICBSYn bit = 1).
(13) Stop condition generator
A stop condition is generated when the IICCn.SPTn bit is set.
(14) Bus status detector
Whether the bus is released or not is ascertained by detecting a start condition and stop condition.
However, the bus status cannot be detected immediately after operation, so set the bus status detector to the
initial status by using the IICFn.STCENn bit.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 540 of 870