UPD70F3741GC Datasheet, PDF (76/889 Pages) Renesas Technology Corp – RENESAS MCU V850ES/JG3 Microcontrollers

V850ES/JG3
CHAPTER 3 CPU FUNCTION
(3) System status register (SYS)
Status flags that indicate the operation status of the overall system are allocated to this register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H R/W Address: FFFFF802H
SYS
0
0
0
0
0
0
PRERR
Detects protection error
0 Protection error did not occur
1 Protection error occurred
<>
0
PRERR
The PRERR flag operates under the following conditions.
(a) Set condition (PRERR flag = 1)
(i) When data is written to a special register without writing anything to the PRCMD register (when <4> is
executed without executing <3> in 3.4.7 (1) Setting data to special registers)
(ii) When data is written to an on-chip peripheral I/O register other than a special register (including execution
of a bit manipulation instruction) after writing data to the PRCMD register (if <4> in 3.4.7 (1) Setting data
to special registers is not the setting of a special register)
Remark
Even if an on-chip peripheral I/O register is read (except by a bit manipulation instruction) between
an operation to write the PRCMD register and an operation to write a special register, the PRERR
flag is not set, and the set data can be written to the special register.
(b) Clear condition (PRERR flag = 0)
(i) When 0 is written to the PRERR flag
(ii) When the system is reset
Cautions 1. If 0 is written to the PRERR bit of the SYS register, which is not a special register,
immediately after a write access to the PRCMD register, the PRERR bit is cleared to 0 (the
write access takes precedence).
2. If data is written to the PRCMD register, which is not a special register, immediately after a
write access to the PRCMD register, the PRERR bit is set to 1.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 60 of 870