UPD70F3741GC Datasheet, PDF (658/889 Pages) Renesas Technology Corp – RENESAS MCU V850ES/JG3 Microcontrollers

V850ES/JG3
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
19.2.2 Restore
(1) From NMI pin input
Execution is restored from the NMI servicing by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the
address of the restored PC.
<1> Loads the restored PC and PSW from FEPC and FEPSW, respectively, because the PSW.EP bit is 0 and the
PSW.NP bit is 1.
<2> Transfers control back to the address of the restored PC and PSW.
The processing of the RETI instruction is shown below.
Figure 19-3. RETI Instruction Processing
RETI instruction
1
PSW.EP
0
PSW.NP
0
PC
PSW
EIPC
EIPSW
1
PC
PSW
FEPC
FEPSW
Original processing restored
Caution When the EP and NP bits are changed by the LDSR instruction during non-maskable interrupt
servicing, in order to restore the PC and PSW correctly during recovery by the RETI
instruction, it is necessary to set the EP bit back to 0 and the NP bit back to 1 using the LDSR
instruction immediately before the RETI instruction.
Remark The solid line shows the CPU processing flow.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 642 of 870