UPD70F3741GC Datasheet, PDF (605/889 Pages) Renesas Technology Corp – RENESAS MCU V850ES/JG3 Microcontrollers

V850ES/JG3
CHAPTER 17 I²C BUS
17.12 Arbitration
When several master devices simultaneously generate a start condition (when the IICCn.STTn bit is set to 1 before the
IICSn.STDn bit is set to 1), communication between the master devices is performed while the number of clocks is
adjusted until the data differs. This kind of operation is called arbitration (n = 0 to 2).
When one of the master devices loses in arbitration, an arbitration loss flag (IICSn.ALDn bit) is set to 1 via the timing by
which the arbitration loss occurred, and the SCL0n and SDA0n lines are both set to high impedance, which releases the
bus (n = 0 to 2).
Arbitration loss is detected based on the timing of the next interrupt request signal (INTIICn) (the eighth or ninth clock,
when a stop condition is detected, etc.) and the setting of the ALDn bit to 1, which is made by software (n = 0 to 2).
For details of interrupt request timing, see 17.7 I²C Interrupt Request Signals (INTIICn).
Figure 17-14. Arbitration Timing Example
Master 1
SCL0n
SDA0n
Master 2
SCL0n
SDA0n
Transfer lines
SCL0n
SDA0n
Remark n = 0 to 2
Hi-Z
Hi-Z
Master 1 loses arbitration
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 589 of 870