UPD70F3741GC Datasheet, PDF (692/889 Pages) Renesas Technology Corp – RENESAS MCU V850ES/JG3 Microcontrollers

V850ES/JG3
CHAPTER 21 STANDBY FUNCTION
(2) Power save mode register (PSMR)
The PSMR register is an 8-bit register that controls the operation status in the power save mode and the clock
operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H R/W Address: FFFFF820H
PSMR
0
0
0
0
0
<>
<>
0
PSM1 PSM0
PSM1
0
0
1
1
PSM0
0
1
0
1
Specification of operation in software standby mode
IDLE1, sub-IDLE modes
STOP, sub-IDLE modes
IDLE2, sub-IDLE modes
STOP mode
Cautions 1. Be sure to clear bits 2 to 7 to “0”.
2. The PSM0 and PSM1 bits are valid only when the PSC.STP bit is 1.
Remark
IDLE1: In this mode, all operations except the oscillator operation and some other circuits (flash
memory and PLL) are stopped.
After the IDLE1 mode is released, the normal operation mode is restored without needing
to secure the oscillation stabilization time, like the HALT mode.
IDLE2: In this mode, all operations except the oscillator operation are stopped.
After the IDLE2 mode is released, the normal operation mode is restored following the
lapse of the setup time specified by the OSTS register (flash memory and PLL).
STOP: In this mode, all operations except the subclock oscillator operation are stopped.
After the STOP mode is released, the normal operation mode is restored following the
lapse of the oscillation stabilization time specified by the OSTS register.
Sub-IDLE: In this mode, all other operations are halted except for the oscillator. After the IDLE mode
has been released by the interrupt request signal, the subclock operation mode will be
restored after 12 cycles of the subclock have been secured.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 676 of 870