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| UPD70F3741GC Datasheet, PDF (623/889 Pages) Renesas Technology Corp – RENESAS MCU V850ES/JG3 Microcontrollers | |||
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V850ES/JG3
CHAPTER 17 I2C BUS
Figure 17-23. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) (2/3)
Processing by master device
IICn
IICn â data
(b) Data
ACKDn
STDn L
SPDn L
WTIMn H
ACKEn H
MSTSn H
STTn L
SPTn L
WRELn L
INTIICn
TRCn H Transmit
Transfer lines
SCL0n 8 9
123456789
SDA0n D0 ACK
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Processing by slave device
IICn
ACKDn
STDn L
SPDn L
WTIMn H
ACKEn H
MSTSn L
STTn L
SPTn L
WRELn
INTIICn
TRCn L Receive
IICn â FFH Note
Note
Note To cancel slave wait, write FFH to IICn or set WRELn.
Remark n = 0 to 2
IICn â data
123
D7 D6 D5
IICn â FFH Note
Note
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 607 of 870
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