UPD70F3741GC Datasheet, PDF (663/889 Pages) Renesas Technology Corp – RENESAS MCU V850ES/JG3 Microcontrollers

V850ES/JG3
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
19.3.3 Priorities of maskable interrupts
The INTC performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being
serviced. Multiple interrupts can be controlled by priority levels.
There are two types of priority level control: control based on the default priority levels, and control based on the
programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control
register (xxICn). When two or more interrupts having the same priority level specified by the xxPRn bit are generated at
the same time, interrupt request signals are serviced in order depending on the priority level allocated to each interrupt
request type (default priority level) beforehand. For more information, see Table 19-1 Interrupt Source List. The
programmable priority control customizes interrupt request signals into eight levels by setting the priority level specification
flag.
Note that when an interrupt request signal is acknowledged, the PSW.ID flag is automatically set to 1. Therefore, when
multiple interrupts are to be used, clear the ID flag to 0 beforehand (for example, by placing the EI instruction in the
interrupt service program) to set the interrupt enable mode.
Remark xx: Identification name of each peripheral unit (see Table 19-2 Interrupt Control Register (xxICn))
n: Peripheral unit number (see Table 19-2 Interrupt Control Register (xxICn)).
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
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