HD404818 Datasheet, PDF (74/100 Pages) Hitachi Semiconductor – 16-digit LCD driver

HD404818 Series
Addressing Modes
RAM Addressing Modes
As shown in figure 39, the MCU has three RAM addressing modes: register indirect addressing, direct
addressing, and memory register addressing.
Register Indirect Addressing Mode: The W register, X register, and Y register contents (10 bits total) are
used as the RAM address.
Direct Addressing Mode: A direct addressing instruction consists of two words, with the word (10 bits)
following the opcode used as the RAM address.
Memory Register Addressing Mode: The memory registers (16 digits from $040 to $04F) are accessed
by executing the LAMR and XMRA instructions.
ROM Addressing Modes and the P Instruction
The MCU has four kinds of ROM addressing modes as shown in figure 40.
Direct Addressing Mode: The program can branch to any address in ROM memory space by executing
the JMPL, BRL, or CALL instruction. These instructions replace the 14 program counter bits (PC₁₃ to PC₀)
with 14-bit immediate data.
Current Page Addressing Mode: The MCU has 32 pages of ROM with 256 words per page. By executing
the BR instruction, the program can branch to an address in the current page. This instruction replaces the
lower eight bits of the program counter (PC₇ to PC₀) with 8-bit immediate data.
When the BR instruction is on a page boundary (256n + 255) (figure 41), executing it transfers the PC
contents to the next page according to the hardware architecture. Consequently, the program branches to
the next page when the BR instruction is used on a page boundary. The HMCS400 series cross
macroassembler has an automatic paging facility for ROM pages.
Zero-Page Addressing Mode: By executing the CAL instruction, the program can branch to the zero-page
subroutine area, which is located at $0000–$003F. When the CAL instruction is executed, 6-bit immediate
data is placed in the lower six bits of the program counter (PC₅ to PC₀) and 0s are placed in the higher eight
bits (PC₁₃ to PC₆).
Table Data Addressing Mode: By executing the TBR instruction, the program can branch to the address
determined by the contents of the 4-bit immediate data, accumulator, and B register.
P Instruction: ROM data addressed by table data addressing can be referenced by the P instruction (figure
42). When bit 8 in the referred ROM data is 1, eight bits of ROM data are written into the accumulator and
B register. When bit 9 is 1, eight bits of ROM data is written into the R1 and R2 port output registers.
When both bits 8 and 9 are 1, ROM data is written into the accumulator and B register, and also to the R1
and R2 port output registers at the same time.
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