HD404818 Datasheet, PDF (25/100 Pages) Hitachi Semiconductor – 16-digit LCD driver

HD404818 Series
Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag enables/disables interrupt requests
(table 4). It is reset by an interrupt and set by the RTNI instruction.
Table 4 Interrupt Enable Flag
IE
Interrupt Enabled/Disabled
0
Disabled
1
Enabled
External Interrupts (INT₀, INT₁): The external interrupt request inputs (INT₀, INT₁) can be selected by
port mode register A (PMRA: $004).
The external interrupt request flags (IF0, IF1) are set at the falling edge of INT₀ and INT₁ inputs,
respectively (table 5).
The INT₁ input can be used as a clock signal input to timer B, in which timer B counts up at each falling
edge of the INT₁ input. When using INT₁ as the timer B external event input, the external interrupt mask
(IM1) has to be set so that the interrupt request by INT₁ will not be accepted (table 6).
More than two instruction cycle times (2t_cyc/2t_subcyc) are needed to detect the edge of INT₀ or INT₁.
External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): The external interrupt request
flags (IF0, IF1) are set at the falling edge of the INT₀ and INT₁ inputs, respectively (table 5).
Table 5 External Interrupt Request Flags
IF0, IF1
0
1
Interrupt Request
No
Yes
External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): The external interrupt masks mask the
external interrupt requests (table 6).
Table 6 External Interrupt Masks
IM0, IM1
0
1
Interrupt Request
Enabled
Disabled (masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): The timer A interrupt request flag is set by the
overflow output of timer A (table 7).
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