HD404818 Datasheet, PDF (65/100 Pages) Hitachi Semiconductor – 16-digit LCD driver

HD404818 Series
Bit 3
80 SEG1
81 SEG2
82 SEG3
83 SEG4
84 SEG5
85 SEG6
86 SEG7
87 SEG8
88 SEG9
89 SEG10
90 SEG11
91 SEG12
92 SEG13
93 SEG14
94 SEG15
95 SEG16
COM4
Bit 2
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
COM3
Bit 1
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
COM2
Bit 0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
COM1
$050
$051
$052
$053
$054
$055
$056
$057
$058
$059
$05A
$05B
$05C
$05D
$05E
$05F
Bit 3
96 SEG17
97 SEG18
98 SEG19
99 SEG20
100 SEG21
101 SEG22
102 SEG23
103 SEG24
104 SEG25
105 SEG26
106 SEG27
107 SEG28
108 SEG29
109 SEG30
110 SEG31
111 SEG32
COM4
Bit 2
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
COM3
Bit 1
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
COM2
Bit 0
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
COM1
$060
$061
$062
$063
$064
$065
$066
$067
$068
$069
$06A
$06B
$06C
$06D
$06E
$06F
Figure 35 Configuration of LCD RAM Area (dual port RAM)
LCD Control Register (LCR: $013): The LCD control register is a 3-bit write-only register which
controls the blanking of the LCD, activation of the power switch, and display in watch mode/subactive
mode (table 27, figure 36).
• Blank/display
Blank: Segment signal is faded regardless of the LCD RAM data.
Display: LCD RAM data is transmitted as a segment signal.
• Power switch on/off
Off: Power switch is off.
On: Power switch is on and V₁ is V_CC.
• Watch mode/subactive mode display
Off: In the watch mode/subactive mode, all common/segment pins are fixed to GND, and the power
switch is off.
On: In the watch mode/subactive mode, LCD RAM data is transmitted as a segment signal.
LCD Duty-Cycle/Clock Control Register (LMR: $014): The LCD duty-cycle/clock control register is a
write-only register which specifies four display duty cycles and the reference clock for the LCD (table 28,
figure 36).
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