HD404818 Datasheet, PDF (33/100 Pages) Hitachi Semiconductor – 16-digit LCD driver

Active mode
Watch mode
HD404818 Series
Oscillation
stabilization period
Active mode
Interrupt strobe
INT₀
Interrupt request
generation
(During the transition
from watch mode to
active mode only)
T
T
t_RC
T_X
T: Interrupt frame length
t_RC: Oscillation stabilization period
Figure 12 Interrupt Frame
Subactive Mode: The CPU operates with a clock generated by the X1 and X2 oscillation circuits.
Functions that can operate in subactive mode are listed in table 16. When the STOP or SBY instruction is
executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of
LSON and DTON. The DTON flag can only be set in subactive mode; it is automatically reset after a
transition to active mode.
Subactive mode is an optional function that the user must specify on the function option list.
Interrupt Frame: In watch and subactive modes, ø_CLK is supplied for timer A and the INT₀ circuit.
Prescaler W and timer A operate as time bases to generate interrupt frame timing. Three interrupt frame
cycles (T) can be selected by the settings of the miscellaneous register, as shown in figure 13.
In watch and subactive modes, timer A and INT₀ interrupts are generated in synchronism with the interrupt
frame. An interrupt request is generated at an interrupt strobe, except when the MCU enters active mode
from watch mode. The INT₀ falling edge is acknowledged regardless of the interrupt frame, but an interrupt
is executed simultaneously with the second interrupt strobe. Timer A generates an overflow and interrupt
request at an interrupt strobe.
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