HD404818 Datasheet, PDF (23/100 Pages) Hitachi Semiconductor – 16-digit LCD driver

Table 3 Interrupt Conditions
Interrupt Control Bit
IE
IF0 • IM0
IF1 • IM1
IFTA • IMTA
IFTB • IMTB
IFTC • IMTC
IFS • IMS
Note: *Don’t care.
Interrupt Source
INT₀
1
INT₁
1
1
0
*
1
*
*
*
*
*
*
*
*
HD404818 Series
Timer A
1
0
0
1
*
*
*
Timer B
1
0
0
0
1
*
*
Timer C
1
0
0
0
0
1
*
Serial
1
0
0
0
0
0
1
Figure 7 shows the interrupt processing sequence, and figure 8 shows the interrupt processing flowchart. If
an interrupt is requested, the instruction being executed finishes in the first cycle. The IE is reset in the
second cycle. In the second and third cycles, the carry flag, status flag, and program counter are pushed
onto the stack. In the third cycle, the instruction is executed after jumping to the vector address.
In each vector address, program the JMPL instruction to branch to the starting address of the interrupt
program. The IF, which caused the interrupt, must be reset by software in the interrupt program.
Instruction
cycles
1
2
3
4
5
6
Instruction
execution
Interrupt
acceptance
Stacking;
reset of IE
Stacking;
vector address
generated
JMPL instruction execution
on the vector address
Figure 7 Interrupt Processing Sequence
Instruction
execution at
starting address
of the interrupt
routine
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