H8SX1651 Datasheet, PDF (720/812 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 20 List of Registers
Register Name
Number of
Abbreviation Bits
Address
Module
Data
Width
Access
Cycles
(Read/Write)
Timer control register_2
TCR_2
8
H'FFFE0 TPU_2
16
2Pφ/2Pφ
Timer mode register_2
TMDR_2
8
H'FFFE1 TPU_2
16
2Pφ/2Pφ
Timer I/O control register_2
TIOR_2
8
H'FFFE2 TPU_2
16
2Pφ/2Pφ
Timer interrupt enable register_2
TIER_2
8
H'FFFE4 TPU_2
16
2Pφ/2Pφ
Timer status register_2
TSR_2
8
H'FFFE5 TPU_2
16
2Pφ/2Pφ
Timer counter_2
TCNT_2
16
H'FFFE6 TPU_2
16
2Pφ/2Pφ
Timer general register A_2
TGRA_2
16
H'FFFE8 TPU_2
16
2Pφ/2Pφ
Timer general register B_2
TGRB_2
16
H'FFFEA TPU_2
16
2Pφ/2Pφ
Timer control register_3
TCR_3
8
H'FFFF0 TPU_3
16
2Pφ/2Pφ
Timer mode register_3
TMDR_3
8
H'FFFF1 TPU_3
16
2Pφ/2Pφ
Timer I/O control register H_3
TIORH_3
8
H'FFFF2 TPU_3
16
2Pφ/2Pφ
Timer I/O control register L_3
TIORL_3
8
H'FFFF3 TPU_3
16
2Pφ/2Pφ
Timer interrupt enable register_3
TIER_3
8
H'FFFF4 TPU_3
16
2Pφ/2Pφ
Timer status register_3
TSR_3
8
H'FFFF5 TPU_3
16
2Pφ/2Pφ
Timer counter_3
TCNT_3
16
H'FFFF6 TPU_3
16
2Pφ/2Pφ
Timer general register A_3
TGRA_3
16
H'FFFF8 TPU_3
16
2Pφ/2Pφ
Timer general register B_3
TGRB_3
16
H'FFFFA TPU_3
16
2Pφ/2Pφ
Timer general register C_3
TGRC_3
16
H'FFFFC TPU_3
16
2Pφ/2Pφ
Timer general register D_3
TGRD_3
16
H'FFFFE TPU_3
16
2Pφ/2Pφ
Note: * When the same output trigger is specified for pulse output groups 2 and 3 by the PCR
setting, the NDRH address is H'FFF7C. When different output triggers are specified, the
NDRH addresses for pulse output groups 2 and 3 are H'FFF7E and H'FFF7C,
respectively. Similarly, When the same output trigger is specified for pulse output
groups 0 and 1 by the PCR setting, the NDRL address is H'FFF7D. When different
output triggers are specified, the NDRL addresses for pulse output groups 0 and 1 are
H'FFF7F and H'FFF7D, respectively.
Rev.2.00 Jun. 28, 2007 Page 696 of 784
REJ09B248-0200