H8SX1651 Datasheet, PDF (404/812 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 9 I/O Ports
Table 9.5 Available Output Signals and Settings in Each Port
Port
P1 6
5
4
2
1
0
P2 7
6
Output
Specification
Signal Name
Output
Signal
Name
Signal Selection
Register Settings
Peripheral Module Settings
DACK1A_OE DACK1 PFCR7.DMAS1[A,B] = DACR.AMS = 1, DMDR.DACKE = 1
00
SCK3_OE
SCK3
When SCMR_3.SMIF = 1:
SCR_3.TE = 1 or SCR_3.RE = 1 while SMR_3.GM = 0,
SCR_3.CKE [1, 0] = 01 or while SMR_3.GM = 1
When SCMR_3.SMIF = 0:
SCR_3.TE = 1 or SCR_3.RE = 1
while SMR_3.C/A = 0, SCR_3.CKE [1, 0] = 01 or
while SMR_3.C/A = 1, SCR_3.CKE 1 = 0
TEND1A_OE
TEND1
PFCR7.DMAS1[A,B] = DMDR.TENDE = 1
00
TxD3_OE
TxD3
SCR.TE = 1
DACK0A_OE DACK0 PFCR7.DMAS0[A,B] = DACR.AMS = 1, DMDR.DACKE = 1
00
SCK2_OE
SCK2
When SCMR.SMIF = 1:
SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0,
SCR.CKE [1, 0] = 01 or while SMR.GM = 1
When SCMR.SMIF = 0:
SCR.TE = 1 or SCR.RE = 1
while SMR.C/A = 0, SCR.CKE [1, 0] = 01 or
while SMR.C/A = 1, SCR.CKE 1 = 0
TEND0A_OE
TEND0
PFCR7.DMAS0[A,B] = DMDR.TENDE = 1
00
TxD2_OE
TxD2
SCR.TE = 1
TIOCB5_OE TIOCB5
TPU.TIOR5.IOB3 = 0, TPU.TIOR5.IOB[1,0] = 01/10/11
PO7_OE
PO7
NDERL.NDER7 = 1
TIOCA5_OE TIOCA5
TPU.TIOR5.IOA3 = 0, TPU.TIOR5.IOA[1,0] = 01/10/11
TMO1_OE
TMO1
TCSR.OS3,2 = 01/10/11 or TCSR.OS[1,0] = 01/10/11
TxD1_OE
TxD1
SCR.TE = 1
PO6_OE
PO6
NDERL.NDER6 = 1
Rev.2.00 Jun. 28, 2007 Page 380 of 784
REJ09B248-0200