H8SX1651 Datasheet, PDF (706/812 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 19 Power-Down Modes
19.9 Bφ Clock Output Control
Output of the Bφ clock can be controlled by bits PSTOP1 and POSEL1 in SCKCR, and DDR for
the corresponding PA7 pin.
Clearing both bits PSTOP1 and POSEL1 to 0 enables the Bφ clock output on the PA7 pin. When
bit PSTOP1 is set to 1, the Bφ clock output stops at the end of the bus cycle, and the Bφ clock
output goes high. When DDR for the PA7 pin is cleared to 0, the Bφ clock output is disabled and
the pin becomes an input port.
Tables 19.3 shows the states of the Bφ pin in each processing state.
Table 19.3 Bφ Pin (PA7) State in Each Processing State
Register Setting Value
DDR
0
1
1
PSTOP1
X
0
0
POSEL1
X
0
1
1
1
X
Normal
Operating Sleep
State
Mode
All-
Software
Module-
Standby Mode
Clock-
Stop Mode OPE = 0 OPE = 1
Hardware
Standby
Mode
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Bφ output Bφ output Bφ output High
High
Hi-Z
Setting Setting Setting Setting Setting Setting
prohibited prohibited prohibited prohibited prohibited prohibited
High
High
High
High
High
Hi-Z
Rev.2.00 Jun. 28, 2007 Page 682 of 784
REJ09B248-0200