H8SX1651 Datasheet, PDF (568/812 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 13 Watchdog Timer (WDT)
13.5 Interrupt Source
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. The OVF flag
must be cleared to 0 in the interrupt handling routine.
Table 13.2 WDT Interrupt Source
Name
WOVI
Interrupt Source
TCNT overflow
Interrupt Flag
OVF
DTC Activation
Impossible
13.6 Usage Notes
13.6.1 Notes on Register Access
The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
(1) Writing to TCNT, TCSR, and RSTCSR
TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a
byte transfer instruction.
For writing, TCNT and TCSR are assigned to the same address. Accordingly, perform data
transfer as shown in figure 13.4. The transfer instruction writes the lower byte data to TCNT or
TCSR.
To write to RSTCSR, execute a word transfer instruction for address H'FFA6. A byte transfer
instruction cannot be used to write to RSTCSR.
The method of writing 0 to the WOVF bit in RSTCSR differs from that of writing to the RSTE bit
in RSTCSR. Perform data transfer as shown in figure 13.4.
At data transfer, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE
bit. To write to the RSTE bit, perform data transfer as shown in figure 13.4. In this case, the
transfer instruction writes the value in bit 6 of the lower byte to the RSTE bit, but has no effect on
the WOVF bit.
Rev.2.00 Jun. 28, 2007 Page 544 of 784
REJ09B248-0200