H8SX1651 Datasheet, PDF (336/812 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 8 Data Transfer Controller (DTC)
Initial
Bit Bit Name Value
R/W
4
DTS
Undefined 
3
DM1
2
DM0
Undefined 
Undefined 
1, 0 
Undefined 
[Legend]
X: Don't care
Description
DTC Transfer Mode Select
Specifies either the source or destination as repeat or
block area during repeat or block transfer mode.
0: Specifies the destination as repeat or block area
1: Specifies the source as repeat or block area
Destination Address Mode 1 and 0
Specify a DAR operation after a data transfer.
0X: DAR is fixed
(DAR writeback is skipped)
10: DAR is incremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
11: SAR is decremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
Reserved
The write value should always be 0.
Rev.2.00 Jun. 28, 2007 Page 312 of 784
REJ09B248-0200