H8SX1651 Datasheet, PDF (548/812 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 12 8-Bit Timers (TMR)
12.4 Operation
12.4.1 Pulse Output
Figure 12.3 shows an example of the 8-bit timer being used to generate a pulse output with a
desired duty cycle. The control bits are set as follows:
1. In TCR, clear bit CCLR1 to 0 and set bit CCLR0 to 1 so that TCNT is cleared at a TCORA
compare match.
2. In TCSR, set bits OS3 to OS0 to B'0110, causing the output to change to 1 at a TCORA
compare match and to 0 at a TCORB compare match.
With these settings, the 8-bit timer provides pulses output at a cycle determined by TCORA with a
pulse width determined by TCORB. No software intervention is required. The output level of the
8-bit timer holds 0 until the first compare match occurs after a reset.
H'FF
TCORA
TCORB
H'00
TMO
TCNT
Counter clear
Figure 12.3 Example of Pulse Output
Rev.2.00 Jun. 28, 2007 Page 524 of 784
REJ09B248-0200