H8SX1651 Datasheet, PDF (581/812 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 14 Serial Communication Interface (SCI)
Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1):
Initial
Bit
Bit Name Value R/W Description
7
GM
0
R/W GSM Mode
Setting this bit to 1 allows GSM mode operation. In
GSM mode, the TEND set timing is put forward to 11.0
etu from the start and the clock output control function
is appended. For details, see sections 14.7.6, Data
Transmission (Except in Block Transfer Mode) and
14.7.8, Clock Output Control.
6
BLK
0
R/W Setting this bit to 1 allows block transfer mode
operation. For details, see section 14.7.3, Block
Transfer Mode.
5
PE
0
R/W Parity Enable (valid only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception. Set this bit to 1 in smart card
interface mode.
4
O/E
0
R/W Parity Mode (valid only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity
1: Selects odd parity
For details on the usage of this bit in smart card
interface mode, see section 14.7.2, Data Format
(Except in Block Transfer Mode).
3
BCP1
0
R/W Basic Clock Pulse 1,0
2
BCP0
0
R/W These bits select the number of basic clock cycles in a
1-bit data transfer time in smart card interface mode.
00: 32 clock cycles (S = 32)
01: 64 clock cycles (S = 64)
10: 372 clock cycles (S = 372)
11: 256 clock cycles (S = 256)
For details, see section 14.7.4, Receive Data Sampling
Timing and Reception Margin. S is described in section
14.3.9, Bit Rate Register (BRR).
Rev.2.00 Jun. 28, 2007 Page 557 of 784
REJ09B248-0200