H8SX1651 Datasheet, PDF (455/812 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.4 Timer Interrupt Enable Register (TIER)
TIER controls enabling or disabling of interrupt requests for each channel. The TPU has six TIER
registers, one for each channel.
Bit
Bit Name
Initial Value
R/W
7
TTGE
0
R/W
6
5
4
3
2
1
0

TCIEU
TCIEV
TGIED
TCIEC
TGIEB
TGIEA
1
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial
Bit
Bit Name value R/W Description
7
TTGE
0
R/W A/D Conversion Start Request Enable
Enables/disables generation of A/D conversion start
requests by TGRA input capture/compare match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
6

1
R
Reserved
This is a read-only bit and cannot be modified.
5
TCIEU 0
R/W Underflow Interrupt Enable
Enables/disables interrupt requests (TCIU) by the TCFU
flag when the TCFU flag in TSR is set to 1 in channels 1,
2, 4, and 5.
In channels 0 and 3, bit 5 is reserved. It is always read as
0 and cannot be modified.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
4
TCIEV 0
R/W Overflow Interrupt Enable
Enables/disables interrupt requests (TCIV) by the TCFV
flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
Rev.2.00 Jun. 28, 2007 Page 431 of 784
REJ09B248-0200