H8SX1651 Datasheet, PDF (19/812 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

12.7 Interrupt Sources............................................................................................................... 530
12.7.1 Interrupt Sources and DTC Activation ............................................................. 530
12.7.2 A/D Converter Activation................................................................................. 530
12.8 Usage Notes ...................................................................................................................... 531
12.8.1 Notes on Setting Cycle...................................................................................... 531
12.8.2 Conflict between TCNT Write and Clear ......................................................... 531
12.8.3 Conflict between TCNT Write and Increment.................................................. 531
12.8.4 Conflict between TCOR Write and Compare Match ........................................ 532
12.8.5 Conflict between Compare Matches A and B................................................... 533
12.8.6 Switching of Internal Clocks and TCNT Operation.......................................... 533
12.8.7 Mode Setting with Cascaded Connection ......................................................... 535
12.8.8 Module Stop Mode Setting ............................................................................... 535
12.8.9 Interrupts in Module Stop Mode....................................................................... 535
Section 13 Watchdog Timer (WDT)..................................................................537
13.1 Features............................................................................................................................. 537
13.2 Input/Output Pin ............................................................................................................... 538
13.3 Register Descriptions........................................................................................................ 538
13.3.1 Timer Counter (TCNT)..................................................................................... 538
13.3.2 Timer Control/Status Register (TCSR)............................................................. 539
13.3.3 Reset Control/Status Register (RSTCSR)......................................................... 540
13.4 Operation .......................................................................................................................... 542
13.4.1 Watchdog Timer Mode ..................................................................................... 542
13.4.2 Interval Timer Mode ......................................................................................... 543
13.5 Interrupt Source ................................................................................................................ 544
13.6 Usage Notes ...................................................................................................................... 544
13.6.1 Notes on Register Access.................................................................................. 544
13.6.2 Conflict between Timer Counter (TCNT) Write and Increment....................... 545
13.6.3 Changing Values of Bits CKS2 to CKS0.......................................................... 546
13.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode............. 546
13.6.5 Internal Reset in Watchdog Timer Mode.......................................................... 546
13.6.6 System Reset by WDTOVF Signal................................................................... 546
13.6.7 Transition to Watchdog Timer Mode or Software Standby Mode.................... 547
Section 14 Serial Communication Interface (SCI) ............................................549
14.1 Features............................................................................................................................. 549
14.2 Input/Output Pins.............................................................................................................. 551
14.3 Register Descriptions........................................................................................................ 552
14.3.1 Receive Shift Register (RSR) ........................................................................... 554
14.3.2 Receive Data Register (RDR) ........................................................................... 554
Rev.2.00 Jun. 28, 2007 Page xix of xxiv