H8SX1651 Datasheet, PDF (306/812 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 7 DMA Controller (DMAC)
Figure 7.22 shows a transfer example when multiple transfer requests from channels 0 to 2.
Bφ
Address bus
DMAC
operation
Wait
Channel 0 transfer
Channel 1 transfer
Channel 2 transfer
Channel 0
Bus
released
Channel 1
Bus
released
Channel 0
Channel 1
Channel 2
Channel 2
Wait
Channel 0
Channel 1
Channel 2
Request cleared
Request cleared
Request Selected
retained
Request Not
Request
retained selected retained
Request cleared
Selected
Figure 7.22 Example of Timing for Channel Priority
Rev.2.00 Jun. 28, 2007 Page 282 of 784
REJ09B248-0200