H8SX1651 Datasheet, PDF (195/812 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 6 Bus Controller (BSC)
6.6.3 Basic Timing
This section describes the basic timing when the data is specified as big endian.
(1) 16-Bit 2-State Access Space
Figures 6.14 to 6.16 show the bus timing of 16-bit 2-state access space.
When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even
addresses access, and the lower byte data bus (D7 to D0) is used for odd addresses. No wait cycles
can be inserted.
Rev.2.00 Jun. 28, 2007 Page 171 of 784
REJ09B248-0200