H8SX1651 Datasheet, PDF (686/812 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 19 Power-Down Modes
Table 19.1 shows conditions for making a transition to a power-down mode, states of the CPU and
peripheral modules, and clearing method for each mode. After the reset state, since this LSI
operates in normal program execution state, the modules other than the DTC or DMAC are
stopped.
Table 19.1 Operating States
Operating State Sleep Mode
All-Module-Clock- Software Standby Hardware
Stop Mode
Mode
Standby Mode
Transition
condition
Cancellation
method
Control register +
instruction
Interrupt
Control register +
instruction
Interrupt*²
Control register +
instruction
External interrupt
Pin input
Oscillator
Functioning
Functioning
Halted
Halted
CPU
Halted (retained) Halted (retained) Halted (retained) Halted
Watchdog timer
8-bit timer
Other peripheral
modules
Functioning
Functioning
Functioning
Functioning
Functioning*⁴
Halted*¹
Halted (retained)
Halted (retained)
Halted*¹
Halted
Halted
Halted*³
I/O port
Functioning
Retained
Retained
Hi-Z
Notes: "Halted (retained)" in the table means that the internal register values are retained and
internal operations are suspended.
1. SCI enters the reset state, and other peripheral modules retain their states.
2. External interrupt and some internal interrupts (8-bit timer and watchdog timer)
3. All peripheral modules enter the reset state.
4. "Functioning" or "Halted" is selectable through the setting of bits MSTPA11 to MSTPA8
in MSTPCRA. However, pin output is disabled even when "Functioning" is selected.
Rev.2.00 Jun. 28, 2007 Page 662 of 784
REJ09B248-0200