HD49343NPHNP_15 Datasheet, PDF (7/23 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49343NP/HNP
Preliminary
Serial Interface Specifications
Serial Interface Specifications
t_INT1
Latches SDATA
CS
at SCK rising edge
f_SCK
Data is determined
at CS rising edge
t_INT2
SCK
t_su
SDATA
t_ho
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
Address
Data
f_SCK
t_INT1,2
t_su
t_ho
Min
—
50 ns
50 ns
50 ns
Max
5 MHz
—
—
—
Notes: 1. Communication is 2 byte continuation communications.
2. Input 16 clocks of SCK while CS is low.
3. Data is invalid if data transmission is aborted during
transmission.
Figure 2 Serial Interface Timing Specifications
Table 1 Serial Data Function List
Address D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
Remarks
PGA gain: –6 to 34dB (0.04dB/step)
D4: LSB, D13: MSB
0
PGA gain
PGA gain
Bias_sel D15, D14: Bias_sel:
0 0 0 0 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 When 0: Biasing regularly, When 1cpdm: biasing
Default value 0 0 0 0 0 0 0 0 0 0 0 0 After 2,3obp: 8clk biasing
Filter
LPF_sel
shsw_sel
sha_fsel slp stby LPF_sel: LPF selection of 5 to 56MHz
1
1 0 0 0 D4 D5 D6
D8 D9 D10 D11 D12 D13 D14 D15 shsw_fsel, sha_fsel; Sampling filter of sp1 part
Default value 1 1 0
0 0 0 1 0 1 0 0 slp, stby: Normally 0 settings
clamp: Setting value × 8+56
Clamp
Polar selection
obp_W: 8clk detection at 0, 4clk detection at 1
2
Polar selection
Reset
clamp
obp
obp pblk Lo-
Re Polar selection; 0 = Negative, 1 = Positive
_W
inv inv pwr calb set Lo-pwr: Guarantee 36MHz at 0, Guarantee 25MHz at 1
0 1 0 0 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 calb: 1 Offset calibration execution
Default value 1 0 0 1 0 0 0 0 0 1 0 1 Reset: Software reset at 0, Normally 1 settings
Dummy clamp
Others
cpdm_th/i: Dummy clamp settings
Dummy clamp
VRT Vref DLL
ADC VRT_sel: 2.0/2.4V switching
3
others
cpdm_th cpdm_i
sel off off
_in Vref_off: Bias off of VRT, VRB
1 1 0 0 D4 D5 D6 D7 D8
D10 D11 D12 D13 D14 D15 ADC_in: ADC input mode at 1
Default value 0 0 0 0 0
000
0
Gray Standard phase: Move between 0 to 3clk
adclk phase: Positive/Negative edge selection
Differential code
Output fixation
10/12: Bit number of gray conversion
4
Standard adclk
differ 10/ Gry test
Gry, difference: On/Off of differential coded gray code
Differential code phase phase Gry ence 12 ref 0 MINV LINV
Gry_ref: 0 = 2 Pixel standard, 1 = 1 Pixel standard
0 0 1 0 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Output fixation: test0, MINV, LINV
Default value 0 0 0 0 0 0 0 0 0 0
(Refer to HD49330 for details)
MON
MON: cp-sw at 0, cpdm at 1
5
1 0 1 0 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
Default value 1 1 0 0 0 0 0 1 0 1 0 0
R19DS0068EJ0200 Rev.2.00
Jul 06, 2012
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