HD49343NPHNP_15 Datasheet, PDF (13/23 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49343NP/HNP
Preliminary
 Dummy clamp (D4 to D8 of address 3)
When a intense highlight like a solar is photoed, light leaks also to the OB part of a sensor and a clamp mistake is
occurred. In order to prevent this incorrect operation, when the level difference of the OB part and a dummy part is
supervised and it becomes the conditions of OB part > dummy part + cpdm_th, it changes to the clamp in a dummy
level automatically. It becomes the amount of current which also set up simultaneously the feedback current at the
time of Dummy on by cpdm_i.
The cpdm pulse for performing a dummy clamp is generated by the following formulas from delay of PBLK.
Cpdm phase = PBLK phase + (address 11)
If a cpdm phase is set as the portion of Shutter noise, it may incorrect-operate. When incorrect operation cannot be
prevented, please turn off a function as cpdm_th = 0.
Moreover, since clamp mistake voltage is also changed by the PGA gain, please control cpdm_th for a gain to be
interlocked with.
sp2
CDS_in
sp1
sp1
SH
amp
VRT
cpdm_i
Current
cell
CDS
–
+
PGA
ADC
OB_DET
–
(Clamp data)
CP-SW
+
DM_DET
cpdm_th
Differential
code
CPDM_Gen
cpdm_dl
Digital
output
OBP
PBLK
cpdm_i
Contents
0 1/4 of current at normal time
1 1/8 of current at normal time
2 1/16 of current at normal time
3 1/32 of current at normal time
cpdm_th Contents
0 Function off
1
+128
2
+256
3
+384
4
+512
5
+640
6
+768
7
+896
Figure 7 Composition of Dummy Clamp Circuit
R19DS0068EJ0200 Rev.2.00
Jul 06, 2012
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