HD49343NPHNP_15 Datasheet, PDF (11/23 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49343NP/HNP
Preliminary
 Clamp high-speed lead-in (D6, D7, D12, D13 of address 6)
If a PGA gain is changed, it will shift to high-speed lead-in operation automatically, and a feedback loop gain will
be controlled by the magnification which set by D6 and D7. During end of the high speed lead-in to returning
normal loop gain, high-speed lead-in mode is continuing until H count number which set by D12, D13. (High-speed
lead-in operation is continuing during offset error is more than 32 LSB, and it returns to normal loop gain in the H
counter number which set by D12, D13 is countered.)
In the usual clamp operation, the open loop differentiation gain (Gain/H) of per 1 H is given by the lower formula.
(1 H is 1 cycle of OBP)
Gain/H = 0.01/(fclk  C3) (fclk: ADCLK frequency, C3: External capacity of FBC)
Ex): fclk = 20 MHz, C3 = 0.1 F  Gain/H = 0.005
DC offset compensation amount per 1 H (LSB) = 0.005  Offset error amount (LSB) *
Note: There is a maximum value in the above-mentioned amount of offset errors.
On the other hand, in high-speed lead-in operation, speed changes as follows.
Ex): fclk = 20 MHz, C3 = 0.1 F  32  Gain/H = 0.16
DC offset compensation amount per 1 H (LSB) = 0.16  Offset error amount (LSB)
When the error of about 500 LSB arises by high-speed lead-in operation, it can lead in a target clamp level by about
20 H.
 Wide_obp (D9 of address 6)
When D9 = 1, it corresponds to wide OBP. When the width of OBP is 63 ± 1 or more clks, it recognizes
automatically that it is wide and detection & compensation is performed every clk. In using this function, please
contact to our company sales.
 OBP_W (D9 of address 2)
Clamp detection is changed to 4 pixels at the time of 8 pixels and D9 = 1 at the time of D9 = 0.
 Each polar selection (D10 to D12 of address 2)
Data
Name
Contents
D11
OBP_inv
Polar selection of OBP.
Input the negative pulse at 0. Input the positive pulse at 1.
D12
PBLK_inv
Polar selection of PBLK
Input the negative pulse at 0. Input the positive pulse at 1.
PBLK_inv is conjunction with SP_inv.
 Low_pwr (D13 of address 2)
It guarantees to sensor clk = 36 MHz at the time of D13 = 0. (HD49343HNP)
It guarantees to sensor clk = 25 MHz at the time of D13 = 1. (HD49343NP)
R19DS0068EJ0200 Rev.2.00
Jul 06, 2012
Page 11 of 22