HD49343NPHNP_15 Datasheet, PDF (5/23 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49343NP/HNP
Preliminary
Electrical Characteristics (cont.)
 Items for CDS_in Mode
(Unless otherwise specified, Ta = 25°C, AV_DD = 3.0 V, DV_DD = 3.0 V)
Item
Symbol
Min
Typ
Max
Unit Test Conditions
Remarks
Consumption current
I_DD1
—
(40)
—
mA f_CLK = 36 MHz
HD49343HNP
I_DD2
—
(25)
—
mA f_CLK = 25 MHz
HD49343NP
CCD offset tolerance range V_CCD
(–150)
—
(150)
mV
Sampling timing
specifications
t_CDS1
t_CDS2
—
Typ  0.8
(1.5)
1/4f_CLK
—
ns
Typ  1.2
ns
Refer to table
4
t_CDS3
t_CDS4
—
Typ  0.8
(1.5)
1/4f_CLK
—
ns
Typ  1.2
ns
t_CDS5
Typ  0.85
1/2f_CLK
Typ  1.0
ns
t_CDS6
—
(5)
—
ns
t_CDS7
11
—
—
ns
t_CDS8
11
—
—
ns
t_CDS9
—
(7)
—
ns
t_CDS10
—
(16)
—
ns
Clamp level
CLP(00)
—
(56)
—
LSB
Clamp level =
CLP(09)
—
(128)
—
LSB
CLP(31)
—
(304)
—
LSB
settings value
 8 + 56
PGA gain at CDS_in
PGA(0)
–8
–6
–4
dB
At 1.0 V input,
PGA(256)
2
4
6
dB
PGA(512)
12
14
16
dB
PGA(768)
22
24
26
dB
PGA(1023)
32
34
36
dB
when PGA
output is 1V, it
is defined as
0dB
Note: Values within parentheses ( ) are for reference.
 Items for ADC_in Mode
Item
Symbol
Min
Typ
Consumption current
I_DD3
—
(30)
I_DD4
—
(20)
Timing specifications
t_ADC1
t_ADC2
t_ADC3
—
Typ  0.85
Typ  0.85
(6)
1/2f_ADCLK
1/2f_ADCLK
t_ADC4
—
(14.5)
t_ADC5
—
(23.5)
Input current at ADC input IIN_CIN
–110
—
Clamp level at ADC input OF2
1848
2048
PGA gain at ADC_in
GSL(0)
–8
–6
GSL(128)
–3
–1
GSL(256)
2
4
GSL(384)
7
9
GSL(511)
12
14
Note: Values within parentheses ( ) are for reference.
Max
—
—
—
Typ  1.15
Typ  1.15
—
—
110
2248
–4
1
6
11
16
Unit Test Conditions
Remarks
mA f_CLK = 36 MHz
mA f_CLK = 25 MHz
ns
ns
ns
ns
ns
A V_IN = 1.0 V to 2.0 V
LSB
dB
At 1.0 V input,
dB
when PGA
dB
output is 1V, it
dB
is defined as
0dB
dB
R19DS0068EJ0200 Rev.2.00
Jul 06, 2012
Page 5 of 22