HD49343NPHNP_15 Datasheet, PDF (14/23 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49343NP/HNP
Preliminary
 VRT_sel (D10 of address 3)
When D10 = 0, VRT is 2.0 V,
when D10 = 1, VRT is 2.4 V are chosen.
However, when set to as D10 = 1, more than in 3.1 V AV_DD voltage as conditions.
VRT_sel
VRT Voltage
CDS Input Range ADC Dynamic Range
0
2.0 V
1.4 Vp-p
1.0 Vp-p
1
2.4 V
2.0 Vp-p
1.4 Vp-p
AV_DD Condition
Min = 2.7 V
Min = 3.1 V
 Vref_off (D11 of address 3)
At the time of D11 = 1, VRB and VRT intercept the supply from the inside of LSI, and the voltage supply from the
outside becomes available.
When making parallel connection, gain variation etc. can be suppressed by setting up as a master/a slave, as shown
in the following figure.
When external supply mode is chosen, please perform an offset calibration in the state of the voltage.
VRT
343
(Master)
Bias VRB
33k
VRT
343
(Slave)
VRB Bias
33k
 ADC_in (D15 of address 3)
When D15 = 0, Normal CDS operation mode,
or when D15 = 1, ADC_in mode for testing (bias is about 1.0 V at this time) are chosen.
 MON (D4 of address 5)
Data
MON Pin
0
cp-sw
1
cpdm
R19DS0068EJ0200 Rev.2.00
Jul 06, 2012
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