HD49343NPHNP_15 Datasheet, PDF (6/23 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49343NP/HNP
Internal Functions
Functional Description
 CDS input
 CCD low-frequency noise is suppressed by CDS (correlated double sampling).
 The signal level is clamped at 56 LSB to 304 LSB by resister during the OB period. *¹
 Gain can be adjusted using 10 bits of register within the range from –6 to 34 dB.
 Automatic offset calibration of PGA and ADC
 DC offset compensation feedback for CCD and CDS
 Pre-blanking
 Digital output is fixed at clamp level.
Note: 1. It is not covered by warranty when 56 LSB settings.
Preliminary
Operating Description
Figure 1 shows function block of this LSI.
ADC_in
CDS_in
sp1
VRT
sp1
sp2
adclk
sp2
LPF
c2
sp1
c1
SH
amp
FBC
c3
ADC_in
CDS
amp
PGA
amp
(Gain setting)
Current
DAC
SHC
12bit
ADC
Offset
calibration
OB clamp
DM clamp
Differential
code
12bit
output
OBP
PBLK
B.G.
ref
CP-SW Bias
VRB
(1.0V)
VRT
(2.0, 2.4V)
Figure 1 Functional Block Diagram of CDS/PGA Part
1. CDS (Correlated Double Sampling) Circuit
The CDS circuit extracts the voltage differential between the black level and a signal level. The black level is
directly sampled at C1 by using the SP2 pulse, buffered by the SHAMP, then provided to the CDSAMP.
The difference between these two signal levels is extracted by the CDSAMP, which also operates as a
programmable gain amplifier at the previous stage.
The CDS input is biased with VRT (2.0 V or 2.4 V)
During the PBLK period, the above sampling and bias operation are paused.
2. PGA Circuit
The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain
using 10 bits of register.
The equation below shows how the gain changes when register value N is from 0 to 1023.
Gain = –6 dB + 0.04 dB  N (Log linear)
3. OB Clamp
Feedback is done to set the black signal level input during the OB period to the DC standard, and all offsets
(including the CCD offset and the CDSAMP offset) are compensated for.
The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged
by the current DAC.
R19DS0068EJ0200 Rev.2.00
Jul 06, 2012
Page 6 of 22