HD49343NPHNP_15 Datasheet, PDF (19/23 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49343NP/HNP
Detailed Timing Specifications at Pre-Blanking
Figure 16 shows the pre-blanking detailed timing specifications.
Preliminary
PBLK
Vth
V_OH
Digital output ADC
(D0 to D11) data
Clamp level
ADC
data
V_OL
ADCLK × 2 clocks
ADCLK × 11 clocks
Figure 16 Detailed Timing Specifications at Pre-Blanking
Detailed Timing Specifications when ADC_in Input Mode is Used
Figure 17 shows the detailed timing chart when ADC_in input mode is used, and table 5 shows each timing
specification.
ADC_in
(2)
ADCLK
D0 to D11
(1)
(3)
(4)
(5)
Vth
V_DD/2
Figure 17 Detailed Timing Chart when ADC_in Input Mode is Used
Table 5 Timing Specifications when ADC_in Input Mode is Used
No.
(1)
(2), (3)
(4)
(5)
Timing
Signal fetch time
ADCLK t_WH min./t_WL min.
ADCLK rising to digital output hold time
ADCLK rising to digital output delay time
Symbol
t_ADC1
t_{ADC2, 3}
t_AHLD4
t_AOD5
Min
—
Typ  0.85
—
—
Typ
(6)
1/2f_ADCLK
(14.5)
(23.5)
Max
—
Typ  1.15
—
—
Unit
ns
ns
ns
ns
R19DS0068EJ0200 Rev.2.00
Jul 06, 2012
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