HD49343NPHNP_15 Datasheet, PDF (10/23 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49343NP/HNP
Preliminary
 SHSW_fsel, SHA_fsel (D8 to D13 of address 1)
Filtering processing is performed to the precharge part sampled by SP1. The cutoff frequency at this time can be
chosen.
Table 1 SHSW Time Constant Setting
SHSW_fsel Data
Cutoff Frequency (MHz)
0
72
1
69
2
63
3
60
4
54
5
51
6
45
7
42
8
36
9
33
10
27
11
24
12
18
13
15
14
9
15
6
Table 2 SHAMP Frequency Characteristics Setting
SHA_fsel Data
Cutoff Frequency (MHz)
0
116
1
75
2
56
3
32
Noise
level
SHSW_fsel
SHA_fsel
Figure 5 The Effect by SHSW_fsel, SHA_fsel
Note: S/N changes with data selections of SHSW_fsel, SHA_fsel, as shown in figure 5. Please find the optimal value
with evaluating a picture.
 SLP and STBY (D14, D15 of address 1)
SLP: Stop the all of circuit. Consumption current should below 10 A at CDS section.
When returning is necessary, please start up from an offset calibration {(3) of figure 6}.
STBY: Operates with only a standard voltage generating circuit. Consumption current is about 3 mA
Please expect about 20 H as time to stabilize a feedback clamp by return.
 Clamp level (D4 to D8 of address 2)
Clamp level = Setting data  8 + 56
D4: LSB, D8: MSB
Default value is set to 9  8 + 56 = 128
R19DS0068EJ0200 Rev.2.00
Jul 06, 2012
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