HD49343NPHNP_15 Datasheet, PDF (15/23 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49343NP/HNP
Preliminary
 Gray code (D4 to D10 of address 4)
ADC output code can be changed by differential coded gray SW (D7, D8) as followings.
D7: 0 Binary code :1 Gray code
D8: 0 Normal :1 Differential code
When switching the several of ADC out put at the same time, ripple (pseudo outline caused by miss quantization)
occurs to the image. Differential code and gray code are recommended for this countermeasure. Figure 8 indicates
circuit block. When luminance signal changes are smoothly, the number of bit of switching digital output bit can be
reduced and easily to reduce the ripple using this function.
This function is especially effective for longer the settings of sensor more than clk = 30 MHz, and ADC output.
In using this code, a complex circuit is needed by the DSP side. Figure 10 indicates the example.
Standard Standard Standard Data Output Timing  adclk phase (D6): ADCLK polarity to OBP
Phase (D4) Phase (D5) at Differential Code Selected
When 0: select positive edge
0
0
Third and fourth (Third)
When 1: select negative edge
1
0
Fourth and fifth (Fourth)
 10/12 (D9): BinaryGray convert bit number
0
1
Fifth and sixth (Fifth)
When 0: select 12 bit
1
1
Sixth and seventh (Sixth)
When 1: select 10 bit
Note: Color filter is different from odd/even pixel, so
considers 2 pixels of a head as a standard. When
 Gry_ref (D10): The number of standard pixel
When 0: select 2 pixel
the inside of ( ) makes a standard 1 pixel.
When 1: select 1 pixel
12 ^{Differential SW (D8)}
ADC
The number of
standard pixel
(D10)
Standard data
control signal
(D4,D5,D6)
2clk_DL
1clk_DL
+
−
Carry bit
rounding
Gray SW (D7)
12
Output
Standard
data
selector
Binary→Gray
conversion
(10/12 bit)
10/12 bit conversion (D9)
Figure 8 Differential code, Gray code Circuit
ADCLK
(In case of select the positive edge of ADCLK by D6)
OBP
(In case of select the
negative polar)
(Falling edge of OBP and standard edge of ADCLK should be exept ±5 ns)
Digital output
12345678
Differential data
Standard
data
Differential data
Figure 9 Timing Specification of Differential code
From ADC
Standard data
control signal
Convert
Gray →
Binary
Carry bit
rounding
Standard
data
selector
2clk
delay
(1) Complex differential coded
D11
D11
D10
D10
D9
D9
D0
D0
(2) Convert Gray → Binary
Figure 10 Complex Circuit Example at the DSP Side
R19DS0068EJ0200 Rev.2.00
Jul 06, 2012
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