HD49343NPHNP_15 Datasheet, PDF (17/23 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49343NP/HNP
Preliminary
Pipeline Delay
The output timing figure at the time of using each input terminal of CDS_in and ADC_in for figure 13 is shown.
0
1
2
~
9
10
11
• CDS_in input mode in use
CDS_in
N
N+1
N+2
N+9
N+10
N+11
SP1
SP2
ADCLK
D0 to D11
N−10
N−9
N−8
N−1
N
• ADC_in input mode in use
N
ADC_in
N+1
N+2
ADCLK
D0 to D11
N−9
N−8
N+10
N+11
N+8
N+9
N−1
N
N+1
Figure 13 Output Timing Figure at the Time of Using Each Input Terminal of CDS_in and ADC_in
 As for an ADC output (D0 to D11), both input mode is outputted by the rising edge of ADCLK.
 The pipeline delay at the time of CDSIN in use is 10 clocks and ADC_in in use is 9 clocks.
 The input signal sampling at the time of ADC_in input mode is performed by the rising edge of ADCLK.
 The pipeline delay increases 1 more clock when using the differential code.
R19DS0068EJ0200 Rev.2.00
Jul 06, 2012
Page 17 of 22